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smsc emc6d103s datasheet revision 0.2 (06-14-06) datasheet product features emc6d103s fan control device with high frequency pwm support and hardware monitoring features ? 3.3 volt operation (5 volt tolerant input buffers) ? smbus 2.0 compliant interface (fixed, not discoverable) with three slave address options ? fan control ? pwm (pulse width modulation) outputs (3) ? fan tachometer inputs (4) ? programmable automatic fan control based on temperature ? backwards compatible with fans requiring lower frequency pwm drive ? high frequency fan support for 4 wire fans ? one fan can be controlled from as many as 3 temperature zones ? fan ramp rate control for acoustic noise reduction ? power savings modes ? two monitoring modes: continuous or cycling (for power savings) ? two low power modes when monitoring if off: sleep and shutdown ? temperature monitor ? monitoring of two remote thermal diodes (+/- 3 deg c accuracy) ? internal ambient temperature measurement ? limit comparison of all monitored values ? interrupt pin for out-of-limit temperature indication ? voltage monitor ? monitors vcc and vccp ? limit comparison of all monitored values ? interrupt pin for out-of-limit voltage indication ? 5 vid (voltage identification) inputs ? xor tree test mode ? 24-pin ssop green, lead-free package order number(s): emc6d103s-czc for 24 pin, ssop package (lead-free) EMC6D103S-CZC-TR for 24 pin, ssop package (lead-free, tape and reel) evaluation board is available
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 2 smsc emc6d103s datasheet 80 arkay drive, hauppauge, ny 11788 (631) 435-6000, fax (631) 273-3123 copyright ? 2006 smsc or its subsidiaries. all rights reserved. circuit diagrams and other information relating to smsc produc ts are included as a means of illustrating typical applications. consequently, complete information sufficient for construction purposes is not necessarily given. although the information has been checked and is believed to be accurate, no re sponsibility is assumed for inaccuracies. smsc reserves the right to make changes to specifications and produc t descriptions at any time without notice. contact your local sm sc sales office to obtain the latest specifications before placing your product order. the provision of this inform ation does not convey to the purchaser of the described semicond uctor devices any licenses under any patent rights or other intellectual property rights of smsc or others. all sales are expressly conditional on your agreement to the te rms and conditions of the most recently dated version of smsc's standard terms of sale agreement dated before the date of your order (the "terms of sale agreement"). the pro duct may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. anomaly sheets are availab le upon request. smsc products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. any and all such uses without prior written approval of an officer of smsc and further testing and/or modification will be fully at the risk of the customer. copies of this document or other smsc literature, as well as the terms of sale agreement, may be obtained by visiting smsc?s website at h ttp://www.smsc.com. smsc is a registered trademark of standard microsystems corporat ion (?smsc?). product names and company na mes are the trademarks of their respective holders. smsc disclaims and excludes any and all warranties, including without limitation any and all implied warranties of merchantabil ity, fitness for a particular purpose, title, and against infringement and the like, and any and all warranties arising from any cou rse of dealing or usage of trade. in no event shall smsc be liable for any direct, incidental, indirect, special, punitive, or cons equential damages; or for lost data, profits, savings or revenues of any kind; regardless of the form of action, whether based on contrac t; tort; negligence of smsc or others; strict liability; breach of warranty; or otherwise; whether or not any remedy of buyer is h eld to have failed of its essential purpose, and whether or no t smsc has been advised of the possibility of such damages.
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 3 revision 0.2 (06-14-06) datasheet table of contents chapter 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 chapter 2 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1 emc6d103s pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 chapter 3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.1 pin functions for emc6d103s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 3.2 buffer type description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.3 3.3v operation, 5v tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 chapter 4 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 maximum guaranteed ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.2 ratings for operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 chapter 5 smbus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 slave address. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.2 slave bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.3 bus protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.4 invalid protocol response behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.4.1 undefined registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.5 general call address response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.6 slave device time-out. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.7 stretching the sclk signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.8 smbus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.9 bus reset sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.10 smbus alert response address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 chapter 6 hardware monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.1 input monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2 resetting the emc6d103s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.1 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.2.2 soft reset (initialization) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3 monitoring modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.3.1 continuous monitoring mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.3.2 cycle monitoring mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.4 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 6.4.1 diode fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6.5 interrupt pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.6 low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6.1 sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.6.2 shutdown mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.7 analog voltage measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.8 voltage id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.9 temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.9.1 internal temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.9.2 external temperature measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.9.3 temperature data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.10 thermal zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 chapter 7 fan control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 4 smsc emc6d103s datasheet 7.1.1 limit and configuration registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1.2 device set-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1.3 pwm fan speed control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 7.1.4 fan speed monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 7.1.5 linking fan tachometers to pwms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 chapter 8 register set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 8.1 undefined registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.2 defined registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.2.1 registers 20-24h: voltage reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.2.2 registers 25-27h: temperature read ing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 8.2.3 registers 28-2fh: fan tachometer reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 8.2.4 registers 30-32h: current pwm duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8.2.5 register 3eh: company id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.2.6 register 3fh: version / stepping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.2.7 register 40h: ready/lock/start monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8.2.8 register 41h: interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 8.2.9 register 42h: interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.2.10 register 43h: vid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 8.2.11 registers 44-4dh: voltage limit re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.2.12 registers 4e-53h: temper ature limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 8.2.13 registers 54-5bh: fan tachometer low limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 8.2.14 registers 5c-5eh: pwm configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 8.2.15 registers 5f-61h: zone temperature range, pwm frequency . . . . . . . . . . . . . . . . . . . 64 8.2.16 register 62h, 63h: pwm ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 8.2.17 registers 64-66h: minimum pwm duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.2.18 registers 67-69h: zone low temperature limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 8.2.19 registers 6a-6ch: absolute temperature limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 8.2.20 register 6f: xor test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 8.2.21 register 7ch: special function register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 8.2.22 register 7eh: interrupt enable 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.2.23 register 7fh: configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8.2.24 register 80h: interrupt enable 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 8.2.25 register 81h: tach_pwm association register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 8.2.26 register 82h: interrupt enable 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 8.2.27 registers 85h-88h: a/d converte r lsbs registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.2.28 registers 90h-93h: tachx option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 8.2.29 registers 94h-96h: pwmx option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 chapter 9 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.1 pwm outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.2 smbus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 chapter 10 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 appendix a adc voltage conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 appendix b example fan circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 5 revision 0.2 (06-14-06) datasheet list of figures figure 2.1 emc6d103s 24 pin ssop pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5.1 address selection on emc6d103s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6.3 interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 7.1 automatic fan control flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 7.2 automatic fan control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 7.4 spin up reduction enabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 7.6 illustration of pwm ramp rate c ontrol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 7.7 pwm and tachometer concept. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 8.11 fan activity above low temp limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 9.1 pwmx output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 figure 9.4 smbus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 10.1 24-pin ssop package outline, 0.150? wide body, 0.025? pitch. . . . . . . . . . . . . . . . . . . . . . 80 figure b.1 fan drive circuitry (apply to pwm driving two fans) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure b.2 fan drive circuitry (apply to pwm driving one fan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure b.3 fan tachometer circuitry (apply to each fan) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 figure b.4 remote diode (apply to remote2 li nes). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 figure b.5 suggested minimum track width and spacing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 6 smsc emc6d103s datasheet list of tables table 3.1 pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 3.2 buffer type descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 5.1 smbus slave address options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5.2 smbus write byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5.3 smbus read byte protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5.4 modified smbus receive byte protocol response to ara. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6.1 avg[2:0] bit decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6.2 conversion cycle timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 6.3 adc conversion sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 6.4 low power mode control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 6.5 min/max adc conversion table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 6.6 temperature data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 7.1 pwm ramp rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 7.2 minimum rpm detectable using 3 edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 7.3 minimum rpm detectable using 2 edges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 8.1 register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 table 8.2 registers 20-24h: voltage reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 8.3 voltage vs. register reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 8.4 registers 25-27h: temperature reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 table 8.5 temperature vs. register reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 8.6 registers 28-2fh: fan tachometer reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 8.7 registers 30-32h: current pwm duty . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 8.8 pwm duty vs register reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 table 8.9 register 3eh: company id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 8.10 register 3fh: version / stepping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 8.11 register 40h: ready/lock/start monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 8.12 ready/lock/start monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 8.13 register 41h: interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 8.15 register 42h: interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 8.17 register 43h: vid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 8.18 registers 44-4dh: voltage limit registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 8.20 registers 4e-53h: temperature limi t registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 8.21 temperature limits vs. register settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 8.22 registers 54-5bh: fan tachometer low limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 table 8.23 registers 5c-5eh: pwm configuratio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 8.24 fan zone setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 8.25 fan spin-up register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 table 8.26 registers 5f-61h: zone temperature range, pwm frequency . . . . . . . . . . . . . . . . . . . . . . . 64 table 8.27 register setting vs. pwm frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 8.28 register setting vs. temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 8.29 register 62h, 63h: min/off, pw m ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 8.30 pwm ramp rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 table 8.31 registers 64-66h: minimum pwm duty cycle. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 8.32 pwm duty vs. register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 8.33 registers 67-69h: zone low temperature limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 8.34 temperature limit vs. register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 8.35 registers 6a-6ch: abso lute temperature limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 table 8.36 absolute limit vs. register setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 8.37 register 6f: xor test register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 table 8.38 register 7ch: special function re gister. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 8.40 avg[2:0] bit decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 table 8.41 register 7eh: interrupt enable 1 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 7 revision 0.2 (06-14-06) datasheet table 8.43 register 7fh: configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 8.45 register 80h: interrupt enable 2 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 8.47 register 81h: tach_pwm association register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 8.50 register 82h: interrupt enable 3 register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 8.52 registers 85h-88h: a/d converter lsbs registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 8.54 registers 94h-96h: pwmx option registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 9.1 timing for pwm[1:3] outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 9.2 smbus timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 10.1 24-pin ssop package para meters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table a.1 analog-to-digital voltage conv ersions for hardware monitoring block. . . . . . . . . . . . . . . . . . 81
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 8 smsc emc6d103s datasheet chapter 1 general description the emc6d103s is an environmental monitoring device with automatic fan control capability. this acpi compliant device provides hardware monitoring for up to fivevoltages and three thermal zones, measures the speed of up to four fans, and controls the speed of multiple dc fans using pulse width modulator (pwm) outputs. high frequen cy and low frequency pwms are supported. the emc6d103s hardware monitor provides analog inputs for monitoring external voltages of +2.5v, +5v, +12v and the processor voltage vccp. this device has the capability to monitor its own internal vcc power supply, which may be connected to eit her main power (vcc) or the suspend power well (vtr). in addition to monitoring the processor voltage, vid inputs are available to identify the voltage specification. external components are not requ ired for voltage scaling or similar treatment. the emc6d103s hardware monitor includes support for monitoring three thermal zones: two external and one internal. the external temperatures are measured via thermal diode inputs capable of monitoring remote devices. in addition, the emc6 d103s is equipped with an ambient temperature sensor for measuring th e internal temperature. pulse width modulators (pwm) control the speed of th e fans by varying the output duty cycle of the pwm. each pwm can be associated with any or all of the thermal zones monitored. as the temperature of the associated zone varies, the pw m duty cycle is adjusted accordingly. the ramp rate control feature controls the rate of chan ge of the pwm output, thereby reducing system noise created by changing the fan speed. the speed of ea ch fan is monitored by a fan tachometer input. the measured values are compared to values stored in limit registers to detect if a fan has stalled or seized. fan speed may be under host software control or automatic. in host control mode, the host software continuously monitors temperature and fan speed r egisters, makes decisions as to desired fan speed and sets the pwm?s to drive the required fan spee d. this device offers an interrupt output signal (int#), which may be used to interrupt the host on out-of-limit temperature or voltage condition enabling an acpi response as opposed to the host software continuously monitoring status. in auto ?zone? mode, the logic continuously monitors t he temperature and fan speeds and adjusts speeds without intervention from the host cpu. fan spe ed is adjusted according to an algorithm using the temperature measured in the sele cted zone, the high and low limits set by the user, and the current fan speed. the emc6d103s supports two monitoring modes: continuous mode and cycle mode. in the continuous monitoring mode, the sampling and conversion process is performed continuously for each voltage and temperature reading after monitoring is enabled. the time for each voltage and temperature reading varies depending on the measurement option. in cy cle monitoring mode, the part completes all sampling and conversions, then waits approximately one second to repeat the process. it repeats the sampling and conversion process typically every 1.2 seconds (1.4 sec max - default averaging enabled). the sampling and conversion of each voltage and temperature reading is performed once every monitoring cycle. (this is a power saving mode.) the emc6d103s can be placed in one of two low-power modes: sleep mode or shutdown mode. these modes do not reset any of the regi sters of the device. in sleep mode bias currents are on and the internal oscillator is on, but the a/d converter and mo nitoring cycle are turn ed off. serial bus communication is still possible with any register in the hardware monitor block while in this low-power mode. in shutdown mode the bias currents are off, th e internal oscillator is off, and the a/d converter and monitoring cycle are turned off. serial communic ation is only possible with a select register.
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 9 revision 0.2 (06-14-06) datasheet chapter 2 pinout 2.1 emc6d103s pinout the emc6d103s is offered in a 24 pin ssop mechanical package. figure 2.1 emc6d103 s 24 pin ssop pinout 24 23 22 21 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 9 10 11 12 sd a sclk vss vcc vid0 vid1 vid2 vid3 vid4 tach3/int# pwm2/int# tach1 tach2 pwm1/xtest out vccp 2.5v 12v 5v remote1+ remote1- remote2+ remote2- tach4/address select pwm3/address enable emc6d103
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 10 smsc emc6d103s datasheet chapter 3 pin description 3.1 pin functions for emc6d103s table 3.1 pin description pin # name function buffer type buffer requirement per function ( note 3.1 ) power well notes hardware monitoring block (24) 1 sda system management bus bi-directional data. open drain output. i m od3 i m od3 vcc 2 sclk system management bus clock. i m i m vcc 5 vid0 voltage id 0 input i m i m vcc 6 vid1 voltage id 1 input i m i m vcc 7 vid2 voltage id 2 input i m i m vcc 8 vid3 voltage id 3 input i m i m vcc 19 vid4 voltage id 4 input i m i m vcc 17 remote1- this is the negati ve analog input (current sink) from the remote thermal diode. this serves as the negative input into the a/d. digital input. i an i an vcc 18 remote1+ this is the posit ive input (current source) from the remote thermal diode. this serves as the positive input into the a/d. i an i an vcc 15 remote2- this is the negati ve analog input (current sink) from the remote thermal diode. this serves as the negative input into the a/d. digital input. i an i an vcc 16 remote2+ this is the posit ive input (current source) from the remote thermal diode. this serves as the positive input into the a/d. i an i an vcc 20 +5v_in analog input for +5v i an i an vcc note 3.2 22 +2.5v_in analog input for +2.5v i an i an vcc note 3.2 23 vccp analog input for +vccp (processor voltage: 0 to 3.0v). i an i an vcc note 3.2 21 +12v_in analog input for +12v i an i an vcc note 3.2
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 11 revision 0.2 (06-14-06) datasheet note: the ?#? as the suffix of a signal name indicates an ?active low? signal. note 3.1 buffer types per function on multiplexed pins are separated by a slash ?/? buffer types in parenthesis represent multiple buffer types for a single pin function. note 3.2 this analog input is backdrive protected. 3.2 buffer type description note: the buffer type values are specified at vcc=3.3v 11 tach1 input for monitoring a fan tachometer input. i m i m vcc 12 tach2 input for monitoring a fan tachometer input. i m i m vcc 9 tach3 /int# input for monitoring a fan tachometer input. /interrupt output to indicate a thermal and/or voltage event. i m od3 i m /od3 vcc 14 tach4 /address select input for monitoring a fan tachometer input. if in address select mode, determines the smbus address of the device. i m i m vcc 24 pwm1 /xtest out pwm output 1 controlling speed of fan. when in xor tree test mode, functions as xor tree output. o8 od8/o8 vcc 10 pwm2 /int# pwm output 2 controlling speed of fan. /interrupt output to indicate a thermal and/or voltage event. od8 od8/od8 vcc 13 pwm3 /address enable# pwm output 3 controlling speed of fan. if pulled to ground at power on, enables address select mode (address select pin controls smbus address of the device). iod8 od8/i vcc 4 vcc positive power supply. nominal 3.3v. vcc is monitored by the hardware monitoring block. (can be powered by +3.3v standby power if monitoring in low power states is required.) 3 vss analog ground. table 3.2 buffer type descriptions buffer type description i m digital input i an analog input, hardware monitoring block i m od3 input/output (open drain), 3ma sink. o8 output, 8ma sink, 4ma source. od8 output (open drain), 8ma sink. io8 input/output, 8ma sink, 4ma source. table 3.1 pin descr iption (continued) pin # name function buffer type buffer requirement per function ( note 3.1 ) power well notes hardware monitoring block (24)
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 12 smsc emc6d103s datasheet 3.3 3.3v operation, 5v tolerance the emc6d103s is intended to operate with a nominal 3.3v power supply. the analog voltage pins are connected to voltage sources at their respective nominal levels. all digital signal pins are 3v switching, but are tolerant to 5v.
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 13 revision 0.2 (06-14-06) datasheet chapter 4 operational description 4.1 maximum guaranteed ratings operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 o c to +70 o c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 o to +150 o c lead temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . refer to jedec spec. j-std-020 maximum v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0v positive voltage on any pin (except for analog inputs), with respect to ground . . . . . . . . . . . . . . 5.5v negative voltage on any pin (except for analog inputs), with respect to ground. . . . . . . . . . . . . . -0.3v positive voltage on voltage analog inputs: vccp_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.5v 2.5v_in . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.0v +5v_in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.0v 12v_in. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17v note: stresses above those listed could cause permane nt damage to the device. this is a stress rating only and functional operation of the devic e at any other condition above those indicated in the operation sections of this specification is not implied. when powering this device from laboratory or system power supplie s, it is important that the absolute maximum ratings not be exceeded or device failure can result. some po wer supplies exhibit voltage spikes on their outputs when the ac power is switched on or off. in addition, voltage transients on the ac power line may appear on the dc output. if this po ssibility exists, it is suggested that a clamp circuit be used. 4.2 ratings for operation ta = 0 o c - 70 o c, vcc=+3.3v 10% parameter symbol min typ max units comments temperature-to-digital converter characteristics internal temperature accuracy external diode sensor accuracy -3 -2 -5 -3 0.25 0.25 +3 +2 +5 +3 o c o c o c o c 0 o c <= t a <= 70 o c 40 o c <= t a <= 70 o c -40 o c <= t s <= 125 o c 40 o c <= t s <= 100 o c
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 14 smsc emc6d103s datasheet notes: ? voltages are measured from the local gr ound potential, unless otherwise specified. ? typical values are at ta=25c and re present most likely parametric norm. analog-to-digit al converter characteristics total unadjusted error differential non-linearity power supply sensitivity total monitoring cycle time (cycle mode, default averaging) conversion time (continuous mode, default averaging) input resistance adc resolution tue dnl pss t c(cycle) t c(cts) 203 1 1 1.22 223 140 2 1.4 248 200 % lsb %/v sec msec k note 4.1 note 4.2 note 4.3 10 bits note 4.6 input buffer (vid0-vid4,tach1-tach4) low input level high input level v ili v ihi 2.0 0.8 vcc+0.3 v v iod type buffer (scl, sda, pwm1, pwm2, pwm3/address enable, int# low input level high input level hysteresis low output level v ili v ihi v hys v ol 2.0 500 0.8 vcc+0.3 0.4 v v mv v i ol = +4.0 ma ( note 4.5 ) leakage current (all - digital) input high current input low current digital input capacitance ileak ih ileak il c in 10 -10 10 a a pf ( note 4.4 ) v in = v cc v in = 0v v cc supply current active mode sleep mode shutdown mode i cc i cc i cc 3 500 3 ma a a all outputs open, all inputs transitioning from/to 0v to/from 3.3v. parameter symbol min typ max units comments
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 15 revision 0.2 (06-14-06) datasheet ? timing specifications are tested at the ttl logic levels, vil=0.4v for a falling edge and vih=2.4v for a rising edge. tri-state output voltage is forced to 1.4v. note 4.1 tue (total unadjusted error) includes offset, gain and linearity errors of the adc. note 4.2 total monitoring cycle time for cycle mode includes a one second delay plus all temperature conversions and all analog input voltage conversions. note 4.3 see table 6.2, ?conversion cycle timing,? on page 22 for conversion cycle timing for all averaging options. only the nominal def ault case is shown in this section. note 4.4 all leakage currents are measured with all pins in high impedance. note 4.5 the low output level for pwm pins is actually +8.0ma. note 4.6 the h/w monitor analog block implements a 10- bit adc. the output of this adc goes to an averager block, which ca n be configured to accumulate the averaged value of the analog inputs. the amount of averaging is programmable. the ou tput of the averaging block produces a 12-bit temperature or volt age reading value. the 8 msbits go to the reading register and the 4 lsbi ts to the a/d lsb register.
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 16 smsc emc6d103s datasheet chapter 5 smbus interface the host processor communicates with the fan moni toring device through a series of read/write registers via the smbus interface. smbus is a serial communication protocol between a computer host and its peripheral devices. 5.1 slave address the default slave address is 0101110b. if this addre ss is desired, the designer should not ground the address enable# pin and should not apply a st rapping resistor to the address select pin. if multiple devices are implemented in a system or another smbus device requires address 0101110b, tach4 and pwm3 must be disabled. in this case, addressing is implemented as follows: the board designer will apply a 10k pull-down resistor to ground on the address enable# pin. upon power up, the emc6d103s device will be placed into address enable mode and assign itself an smbus address according to the address select input. the device will latch the address during the first valid smbus transaction in which the first five bits of the targeted address match those of the emc6d103s address. this feature eliminates the possibility of a glitch on the smbus interfering with address selection. in this way, there can be up to three emc6d103s devices on the smbus at any time. multiple emc6d103s devices can be used to monitor additional processors and temperature zones. table 5.1 smbus slave address options address enable# address select board implementation smbus address [7:1] 1 x address enable# pulled to vcc through resistor note: resistor value will be dependent on pwm circuit implemented. 0101 110b (default) 0 0 address enable# pulled to ground through 10k resistor address select pulled to ground through a 10k resistor 0101 100b 0 1 address enable# pulled to ground through 10k resistor address select pulled to vcc through a 10k resistor 0101 101b
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 17 revision 0.2 (06-14-06) datasheet figure 5.1 address selection on emc6d103s 5.2 slave bus interface the emc6d103s device smbus implementation is a subset of the smbus interface to the host. the device is a slave-only smbus device. the implementation in the device is a subset of smbus since it only supports write byte and read byte protocols. the write byte and read byte protocols are valid smbus protocols for the device. this part responds to other protocols as described in the invalid pr otocol section. reference the system management bus specification, rev 2.0. the smbus interface is used to read and write the re gisters in the device. the register set is shown in chapter 8, "register set," on page 47 . 5.3 bus protocols typical write byte and read byte protocols are shown below. register accesses are performed using 7-bit slave addressing, an 8-bit register address fiel d, and an 8-bit data field. the shading indicates the hardware monitor block driving data on the sda line; otherwise, host data is on the sda line. the slave address is the unique smbus interface address for the hardware monitor block that identifies it on smbus. the register address field is the internal address of the register to be accessed. the register data field is the data that the host is at tempting to write to the register or the contents of the register that the host is attempting to read. note: data bytes are transferred msb first. byte protocols a write byte transfer will always consist of the smbu s interface address byte, followed by the internal address register byte, then the data byte. the normal read protocol consists of a write to the hardware monitor block with the smbus interface address byte, followed by the internal address r egister byte. then restart the serial communication with a read consisting of the smbus interface addre ss byte, followed by the data byte read from the hardware monitor block. this can be acco mplished by using the read byte protocol. write byte the write byte protocol is used to write data to the registers. the data will only be written if the protocol shown in table 5.2 is performed correctly. only one byte is tr ansferred at time for a write byte protocol. start s da scl address decided first five address bits 0 1 0 1 1
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 18 smsc emc6d103s datasheet read byte the read byte protocol is used to read data from the registers. the data will only be read if the protocol shown in ta b l e 5 . 3 is performed correctly. only one byte is transferred at time for a read byte protocol. 5.4 invalid protocol response behavior registers that are accessed with an invalid protocol will not be updated. a regi ster will only be updated following a valid protocol. the only valid protocols are the write byte and read byte protocols, which are described above. the emc6d103s device responds to three smbus slave addresses: 1. the smbus slave address that supports the valid protocols defined in the previous sections is determined by the level on the address select and address enable pins as shown in section 5.1, "slave address," on page 16 . 2. smbus alert response (0001 100). the smbus will only respond to the smbus alert response address if the smbus alert respon se interrupt was generated to request a response from the host. the smbus alert response is defined in section 5.10, "smbus al ert response address," on page 19 . attempting to communicate with the hardware monitor block over smbus with an invalid slave address, or invalid protocol will result in no response, and the smbus slave interface will return to the idle state. the only valid registers that are accessible by t he smbus slave address are the registers defined in the registers section. see section 5.4.1, "undefined registers" for response to undefined registers. 5.4.1 undefined registers reads to undefined registers return 00h. writes to undefined registers have no effect and return no error. 5.5 general call address response the emc6d103s will not respond to a general call address of 0000_000. 5.6 slave device time-out the emc6d103s supports the slave device timeout as per the smbus specification, v2.0. table 5.2 smbus write byte protocol field start slave addr wr ack reg. addr ack reg. data ack stop bits 171181811 table 5.3 smbus read byte protocol field: start slave addr wr ack reg. addr ack start slave addr rd ack reg. data nack stop bits: 1711811711811
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 19 revision 0.2 (06-14-06) datasheet according to smbus specification, v2.0 devices in a transfer can abort the transfer in progress and release the bus when any single clock low interval exceeds 25ms (t timeout, min ). devices that have detected this condition must reset their communica tion and be able to receive a new start condition no later than 35ms (t timeout, max ). note: some simple devices do not contain a clock low drive circuit; this simple kind of device typically may reset its communications port after a start or stop condition 5.7 stretching the sclk signal the emc6d103s supports stretching of the sclk by other devices on the smbus but will not stretch the sclk itself. 5.8 smbus timing the smbus slave interface complie s with the smbus ac timing specification. see the smbus timing diagram shown in the section titled section 9.2, "smbus interface," on page 79 . 5.9 bus reset sequence the smbus slave interface will reset and return to the idle state upon a start field followed immediately by a stop field. 5.10 smbus alert response address the emc6d103s device responds to the smbus alert res ponse address, 0001 100, if the inten bit (register 7ch bit 2) is set and one or more status events bits are high. the interrupt signal (int#), which can be enabled on either the pwm2 or tach3 pins, can be used as the smbalert#. see the section describing the interrupt status registers on page 24 and the section describing the interrupt pin on page 26 for more details on interrupts. the device can signal the host that it wants to talk by pulling the smbalert# low, if a status bit is set in one of the interrupt status registers and pro perly enabled onto the int# pin. the host processes the interrupt and simultaneously accesses all smbalert# devices through a modified receive byte operation with the alert response address (ara). the emc6d103s device, which pulled smbalert# low, will acknowledge the alert response address and respond with its device address. th e 7-bit device address provided by the emc6d103s device is placed in the 7 most significant bits of the byte. the eighth bit can be a zero or one. after acknowledging the slave address, the emc6d103s device will disengage the smbalert# pull- down by clearing the int enable bit. if the condition that caused the interrupt remains, the fan control device will reassert the smbalert# on the next monitoring cycle, provided the int enable bit has been set back to ?1? by software. note: the int# signal is an alternate function on the pwm2 and tach3 pins. the emc6d103s device will respond to the smbus alert response address even if the int# signal is not selected as the alternate function on one of these pins as lo ng as the following conditions exist: the inten table 5.4 modified smbus receiv e byte protocol response to ara field: start alert response address rd ack emc6d103s slave address nack stop bits: 1711 8 11
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 20 smsc emc6d103s datasheet bit (register 7ch bit 2) is set, an individual status bit is set in one of the interrupt status registers, and the corresponding group enable bit is set. each interrupt event must be enabled into the interrupt status registers, and the status bits must be enabled onto the int# signal via the group enable bits for each type of event (i.e., temperature, voltage and fan). see the section titled interrupt status registers on page 24 .
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 21 revision 0.2 (06-14-06) datasheet chapter 6 hardware monitoring the following sub-sections describe the emc6d103s hardware monitoring features. 6.1 input monitoring the emc6d103s device?s monitoring function is started by writing a ?1? to the start bit in the ready/lock/start register (0x40). measured values from th e analog inputs and temperature sensors are stored in reading registers. the values in the reading registers can be accessed via the smbus interface. these values are compared to the progr ammed limits in the limit register. the out-of-limit and diode fault conditions are stored in the interrupt status registers. 6.2 resetting the emc6d103s 6.2.1 power-on reset all the registers in the hardware monitor block, e xcept the reading registers, reset to a default value when power is applied to the block. the default state of the register is shown in the table in the register summary subsection. the default state of reading registers are not shown because these registers have indeterminate power on values. note: usually the first action after power up is to write limits into the limit registers. 6.2.2 soft reset (initialization) setting bit 7 of the conf register performs a soft re set. this bit is self-clearing. soft reset performs reset on all the registers except the reading registers. 6.3 monitoring modes the hardware monitor block supports two monitoring modes: continuous mode and cycle mode. these modes are selected using bit 1 of the special function register (7ch). the following subsections contain a description of these monitoring modes. the hardware monitor conversion clock is 45khz 10%. temperature conversions take 96 clocks, each (2.133ms nom.); voltage conversions take 68 clocks, each (1.511ms nom). the time to complete a conversion cycle depe nds upon the number of inputs in t he conversion sequence to be measured (see table 6.3, ?adc conversion sequence,? on page 23 ) and the amount of averaging per input, which is selected using the avg[2:0] bits in the special function register (see register 7ch: special function register on page 70 ). for each mode, there are four options for the num ber of measurements that are averaged for each temperature and voltage reading. these options are selected using bits[7:5] of the special function register (7ch). these bi ts are defined as follows: bits [7:5] avg[2:0] the avg[2:0] bits determine the amount of averaging for each of t he measurements that are performed by the hardware monitor before the reading registers are updated ( ta b l e 6 . 1 ). the avg[2:0] bits are priority encoded where the most significant bit has hi ghest priority. for example, when the avg2 bit is asserted, 32 averages will be performed for each measurement before the reading registers are updated regardless of the stat e of the avg[1:0] bits.
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 22 smsc emc6d103s datasheet note: the default for the avg[2:0] bits is ?010?b. to calculate conversion cycle timing for a given averaging mode: ? compute total number of temper ature conversions (temp_conv) ? compute total number of voltage conversions (volt_conv) ? calculate time to complete all conversions is: total conversion time = (temp_conv)*96/(45 khz +/-10%)+ (volt_co nv)*68/(45khz +/-10%) example: to calculate the nominal co nversion time for avg[2:0] = 001b. total conversion time = (temp_conv )*96/(45khz)+ (volt_conv)*68/(45khz) total conversion time = (16+16+1)*96/(45khz)+ (5*1)*68/(45khz) total conversion time = (33)*2.133ms+ (5)*1.511ms = ~78ms table 6.2 illustrates the min., nom., and max. conversion cycle timing for each of the four averaging modes. note 6.1 the hardware monitor conversion clock is 45khz 10%. note 6.2 temperature conversions take 96 clocks, each (2.133ms nom.); voltage conversions take 68 clocks, each (1.511ms nom). table 6.1 avg[2:0] bit decoder sftr[7:5] measurements per reading avg2 avg1 avg0 remote diode 1 remote diode 2 internal diode all voltage readings (+2.5v, +5v, +12v, vccp, and vcc) 000 128 128 8 8 0 0 1 16 16 1 1 01x161616 16 1xx323232 32 table 6.2 conversion cycle timing avg[2:0] total temperature conversions total voltage conversions conversion cycle time (msec) min. nom. max. 000 (2x128)+(1x8)=264 5x8=40 567 624 693 001 (2x16)+(1x1)=33 5x1=10 71 78 87 01x (default) 3x16=48 5x16=80 203 223 248 1xx 3x32=96 5x32=160 406 447 496
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 23 revision 0.2 (06-14-06) datasheet 6.3.1 continuous monitoring mode in the continuous monitoring mode, the sampling and conversion process is performed continuously for each voltage and temperature reading after the start bit is set high. the time for each voltage and temperature reading is shown abov e for each measurement option. the continuous monitoring function is started by doing a write to the ready/lock/start register, setting the start bit (bit 0) high. the part then performs a ?round robin? sampling of the inputs, in the order shown below (see ta b l e 6 . 3 ). sampling of all values occurs in a nominal 223 ms (default - see table 6.2, ?conversion cycle timing,? on page 22 ). when the continuous monitoring function is started, it cycles through each measurement in sequence, and it continuously loops thr ough the sequence approximately onc e every 223 ms (default - see table 6.2, ?conversion cycle timing,? on page 22 ). each measured value is compared to values stored in the limit registers. when the measured value violates the programmed lim it the hardware monitor block will set a corresponding status bit in the interrupt status registers. if auto fan option is selected, the hardware will adj ust the operation of the fans accordingly. see auto fan control operating mode on page 33 . the results of the sampling and conversions can be found in the reading registers and are available at any time. 6.3.2 cycle monitoring mode in cycle monitoring m ode, the part comple tes all sampling and conversions, then waits approximately one second to repeat the process. it repeats the sa mpling and conversion process typically every 1.2 seconds (1.4 sec max - default averaging enabled). the sampling and conversion of each voltage and temperature reading is performed once every monitoring cycl e. this is a pow er saving mode. the cycle monitoring fu nction is started by doing a write to the ready/lock/st art register, setting the start bit (bit 0) high. the part t hen performs a ?round robin? sampling of the inputs, in the order shown above. when the cycle monitoring function is started, it cy cles through each measurement in sequence, and it produces a converted voltage and temperature reading for each i nput. the state machine waits approximately one second before repeating this proc ess. each measured value is compared to values stored in the limit registers. when the measured value violates (or is equal to) the programmed limit the hardware monitor block will set a corresponding status bit in the interrupt status registers. if auto fan option is selected, the hardware will ad just the operation of the fans accordingly. see the section titled auto fan control operating mode on page 33 . table 6.3 adc conversion sequence sampling order register 1 remote diode temp reading 1 2 ambient temperature reading 3 vcc reading 4 +12v reading 5+5v reading 6 +2.5v reading 7 vccp (processor) reading 8 remote diode temp reading 2
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 24 smsc emc6d103s datasheet the results of each sampling and conversion can be found in the reading registers and are available at any time, however, they are only updated once per conversion cycle. 6.4 interrupt status registers the hardware monitor block contains two interrupt status registers: register 41h: interrupt status register 1 on page 57 and register 42h: interrupt status register 2 on page 58 . these registers are used to reflect the state of all te mperature, voltage and fan violation of limit error conditions and diode fault conditions that the hard ware monitor block monitors. when an error occurs during the conversion cycle, its co rresponding bit is set in its respective interrupt status register. the bit remains set until the register is read by software, at which time the bit will be cleared to ?0? if the associated error event no longer violates the limit conditi ons or if the diode fault condition no longer exists. reading the register will not cause a bit to be cleared if the source of the status bit remains active. these registers are read only ? a write to these registers have no effect. these registers default to 0x00 on vcc por and initialization. see the description of the interrupt status registers in chapter 8, "register set," on page 47 . each interrupt status bit has a corresponding bit located in an interrupt enable register, which may be used to enable/disable the individual event from setti ng the status bit. see the following figure for the status and enable bits used to control the interrupt bits and int# pin.
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 25 revision 0.2 (06-14-06) datasheet figure 6.3 interrupt control note: the diode fault bits are not mapped directly to th e int# pin. a diode fault condition forces the diode reading register to a value of 80h, which will generate a diode error condition. see section diode fault on page 25 . 6.4.1 diode fault the emc6d103s chip automatically sets the associated diode fault bit to 1 when any of the following conditions occur on the remote diode pins: ? the positive and negative terminal are an open circuit. ? positive terminal is connected to vcc ? positive terminal is connected to ground ? negative terminal is connected to vcc ? negative terminal is connected to ground the occurrence of a fault will cause 80h to be loaded into the associated reading register, except for the case when the negative terminal is connected to ground. a temperature r eading of 80h will cause int_sts1 reg 12v_error (int2[0]) diode 2 fault (int2[7]) diode 1_en (ier3[2]) diode 2_en (ier3[3]) diode 1 fault (int2[6]) int2 (int1[7]) int_sts2 reg diode 1 fault 12v_error_en (ier1[6]) 12v_error diode 2 fault 2.5v_error (int1[0]) 2.5v_error_en (ier1[2]) 2.5v_error vccp_error (int1[1]) vccp_error_en (ier1[3]) vccp_error vcc_error (int1[2]) vcc_error_en (ier1[7]) vcc_error 5v_error (int1[3]) 5v_error_en (ier1[5]) 5v_error diode 1 limit (int1[4]) diode 1_en (ier3[2]) diode 1 limit diode 2 limit (int1[6]) diode 2_en (ier3[3]) diode 2 limit ambient limit ambient limit (int1[5]) ambient_en (ier3[1]) tach1 (int2[2]) tach1_en (ier2[1]) tach1 out-of-limit tach2 (int2[3]) tach2 _en (ier2[2]) tach2 out-of-limit tach3 (int2[4]) tach3 _en (ier2[3]) tach3 out-of-limit tach4 (int2[5]) tach4 _en (ier2[4]) tach4 out-of-limit + tach_en (ier2[0]) voltage_en (ier1[0]) temp_en (ier3[0]) + + + int# int_en (sftr[2])
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 26 smsc emc6d103s datasheet the corresponding diode error bit to be set. this will cause the int# pin to become active if the individual, group (temp), and global enable (inten) bits are set. notes: ? the individual remote diode enable bits and the temp bit are located in table 8.51 on page 74 . the inten bit is located in bit[2] of register 7ch: special function register on page 70 . ? when 80h is loaded into the remote diode reading register the pwm output(s) controlled by the zone associated with that diode inpu t will be forced to full on. see thermal zones on page 30 . if the diode is disabled, the fault bit in the interrupt status register will not be set. in this case, the occurrence of a fault will cause 00h to be loaded in to the associated reading register. the limits must be programmed accordingly to prevent unwanted fan speed changes based on this temperature reading. if the diode is disabled and a fault condi tion does not exist on the diode pins, then the associated reading register will contain a ?valid? reading. 6.5 interrupt pin the int# function is used as an interrupt output for out-of-limit temperature, vo ltage events, and/or fan errors. ? the int# signal can be enabled onto the pwm2 or the tach3 pins. to configure the pwm2/int# pin fo r the interrupt function, set bit[ 1] p2int of the conf register (7fh) to ?1? to configure the tach3/int# pin for the interrupt function, set bit[0] t3int of the conf register (7fh) to ?1? ? to enable the interrupt pin to go active, set bit 2 of the special function register (7ch) to ?1?. to enable temperature event, voltage even ts and/or fan events onto the int# pin: ? to enable out-of-limit temperature events set bit[0] of the interrupt enable 3 (temp) register (82h) to ?1?. ? to enable out-of-limit voltage events set bit[0] of the interrupt enable 1(volt) register (7eh) to ?1? ? to enable fan tachometer error events set bit[0] of the interrupt enable 2(fan tachs) register (80h) to ?1?. see figure 6.3 on page 25 . the following description assumes that the interrupt enable bits for all events are set to enable the interrupt status bits to be set. if the internal or remote temperature reading violates the low or high temperature limits, int# will be forced active low (if all the corresponding enable bits are set: individual enable bits (d1_en, d2_en, and/or amb_en), group enable bit (temp_en) and the global enable bit (inten)). this pin will remain low while the internal temp error bit or one or both of the remote temp error bits in interrupt status 1 register is set and the enable bit is set. the int# pin will not become active low as a result of the remote diode fault bits becoming set. however, the occurrence of a fault will cause 80h to be loaded into the associated reading register, which will cause the corresponding diode error bit to be set. this will cause the int# pin to become active if enabled. the int# pin can be enabled to indicate out-of-limit voltages. bit[0] of the interrupt enable 1(volt) register (7eh) is used to enable this option. when this bit is set, if one or more of the voltage readings violates the low or high limits, int# will be forced active low (if all the corresponding enable bits are set: individual enable bits (vcc_error_en, vccp_error_en,12v_error_en, 5v_error_en, 33v_error_en, 25v_error_en, 18v_error_en, and/ or 15v_error_en), group enable (volt_en), and global enable (int_en)). this pin will remain low while the associated voltage error bit in the interrupt status register 1 or interrupt status register 2 is set.
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 27 revision 0.2 (06-14-06) datasheet the int# pin can be enabled to indicate fan errors. bit[0] of the interrupt en able 2(fan tachs) register (80h) is used to enable this option. this pin will remain low while the associated fan error bit in the interrupt status register 2 is set. the int# pin will remain low while any bit is set in any of the interrupt status registers. reading the interrupt status registers will cause the logic to atte mpt to clear the status bits; however, the status bits will not clear if the interrupt stimulus is still acti ve. the interrupt enable bit (special function register bit[2]) should be cleared by software before reading the interrupt status registers to insure that the int# pin will be re-asserted while an interrupt event is active , when the int_en bit is written to ?1? again. the int# pin can also be deasserted by issuing an alert response address call. see the description in the section titled smbus alert response address on page 19 . the int# pin may only become active while the monitor block is operational. 6.6 low power modes the hardware monitor block can be placed in a low-power mode by writing a ?0? to bit[0] of the ready/lock/start register (0x40). the low power mode that is entered is either sleep mode or shutdown mode as selected using bit[0] of the sp ecial function register (7ch). these modes do not reset any of the registers of the hardware monitor block. in both of these modes, the pwm pins are at 100% duty cycle. notes: ? start and lpmd bits cannot be modified when the lock bit is set. ? start bit is located in the read y/lock/start register (40h). lpmd bit is located in the special function register (7ch) 6.6.1 sleep mode this is a low power mode in which bias currents ar e on and the internal oscillator is on, but the a/d converter and monitoring cycle are turned off. serial bus communication is still possible with any register in the hardware monitor bl ock while in this low-power mode. 6.6.2 shutdown mode this is a low power mode in which bias currents are off, the internal oscillator is off, and the the a/d converter and monitoring cycle are tu rned off. serial communication is only possible with bits[2:0] of the special function register at 7ch and bits [7:0] of the configuration register at 7fh, which become write-only registers in this mode. 6.7 analog voltage measurement the hardware monitor block contains inputs for directly monitoring the power supplies (+12 v, +5 v, +2.5v, vccp, and vcc). these inputs are scaled inte rnally to an internal reference source, converted via an 8 bit successive approximation register adc , and scaled such that the correct value refers to 3/4 scale or 192 decimal. the vccp input is scaled for a full range of 0v to 3v. this removes the need for external resistor dividers and allows for a more accurate means of measurement since the voltages are referenced to a known value. since any of these inputs can be table 6.4 low power mode control bits start lpmd description 0 0 sleep mode 0 1 shutdown mode 1 x monitoring
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 28 smsc emc6d103s datasheet above vcc or below ground, they are not diode protected to the power rails. the measured values are stored in the reading registers and compared wit h the limit registers. the status bits in the interrupt status register 1 and 2 are set if th e measured values violate the programmed limits. the vccp voltage input measures the processor vo ltage, which will lie in the range of 0v to 3.0v. table 6.5, "min/max adc conversion table" shows the values of the analog inputs that correspond to the min and max output codes of the a/d converter. for a complete list of the adc conversions see appendix a, "adc voltage conversion," on page 81 . 6.8 voltage id vid0-vid4 digital inputs are used to store processor voltage id codes (for processor operating voltage) in the vid0-4 regist er (43h). these vids can be read out by the management syst em using the smbus interface. 6.9 temperature measurement temperatures are measured internally by bandgap temperature sensor and externally using two sets of diode sensor pins (for measuring two ex ternal temperatures). see subsections below. note: the temperature sensing circuitry for the two remote diode sensors is calibrated for a 3904 type diode. 6.9.1 internal temperature measurement internal temperature can be measured by bandgap temperature sensor. the measurement is converted into digital format by in ternal adc. this data is convert ed in two?s complement format since both negative and positive temperature can be measured. this value is stored in internal temperature reading register (26h) and compared to the temperature limit registers (50h ? 51h). if this value violates the programmed limits in the internal high temperature limit register (51h) or the internal low temperature limit register (50h) the corresponding st atus bit in interrupt status register 1 is set. if auto fan option is selected, the hardware will ad just the operation of the fans accordingly. see the section titled auto fan control operating mode on page 33 . 6.9.2 external temperature measurement the hardware monitor block also provides a way to measure two external temperatures using diode sensor pins (remote x+ and remote x-). the value is stored in the register (25h) for remote1+ and remote1- pins. the value is stored in the remote temperature reading register (27h) for remote2+ and remote2- pins. if these values violate the programmed limits in t he associated limit registers, then the corresponding remote diode 1 (d1) or remote diode 2 (d2) status bits will be set in the interrupt status register 1. if auto fan option is selected, the hardware will adj ust the operation of the fans accordingly. see auto fan control operating mode on page 33 . table 6.5 min/max adc conversion table input voltage +12v in +5v in v cc /3.3v in +2.5v in +1.8v in +1.5v in +v ccp min value (corresponds to a/d output 00000000) <0.062 <0.026 <0.017 <0.013 <0.009 <0.008 <0.012 max value (corresponds to a/d output 11111111) >15.938 >6.640 >4.383 >3.320 >2.391 >1.992 >2.988
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 29 revision 0.2 (06-14-06) datasheet there are remote diode (1 or 2) fault status bits in interrupt status register 2 (42h), which, when set to a logical ?1?, indicate a short or open-circuit on remote thermal diode inputs (remote x+ and remote x-). before a remote diode conversion is updated, th e status of the remote diode is checked. in the case of a short or open-circuit on the remote thermal diode inputs, the value in the corresponding reading register will be forced to 80h. note that this will cause the associated remote diode limit exceeded status bit to be set (i.e. remote diode x limit error bits (d1 and d2) are located in the interrupt status 1 register at register address 41h). the temperature change is computed by measuring the change in vbe at two different operating points of the diode to which the remote x+ and remote x- pins are connected. but accuracy of the measurement also depends on non-ideality factor of the process the diode is manufactured on. 6.9.3 temperature data format temperature data can be read from the three temperature registers: ? internal temp reading register (26h) ? remote diode 1 temp reading register (25h) ? remote diode 2 temp reading register (27h) table 6.6, "temperature data format" shows several examples of the format of the temperature digital data, represented by an 8-bit, two?s comple ment word with an lsb equal to 1.0 0 c. table 6.6 temperature data format temperature reading (dec) reading (hex) digital output -127 0 c -127 81h 1000 0001 ? ? ? ? -50 0 c -50 ceh 1100 1110 ? ? ? ? -25 0 c -25 e7h 1110 0111 ? ? ? ? -1 0 c -1 ffh 1111 1111 0 0 c 0 00h 0000 0000 +1 0 c 1 01h 0000 0001 ? ? ? ? +25 0 c 25 19h 0001 1001 ? ? ? ? +50 0 c 50 32h 0011 0010 ? ? ? ? +127 0 c 127 7fh 0111 1111 sensor error 128 80h 1000 0000
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 30 smsc emc6d103s datasheet 6.10 thermal zones each temperature measurement input is assigned to a thermal zone to control the pwm outputs in auto fan control mode. these zone assignments are as follows: ? zone 1 = remote diode 1 (processor) ? zone 2 = ambient (internal) temperature sensor ? zone 3 = remote diode 2
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 31 revision 0.2 (06-14-06) datasheet chapter 7 fan control the following sections describe the various fan control and monitoring modes in the part. 7.1 general description this fan control device is capable of driving mu ltiple dc fans via three pwm outputs and monitoring up to four fans equipped with tachometer outputs in either manual fan control mode or in auto fan control mode. the three fan control outputs (pwmx pins) are controlled by a pulse width modulation (pwm) scheme. the four pins dedicated to moni toring the operation of eac h fan are the tach[1:4] pins. fans equipped with fan tachometer outputs may be connected to these pins to monitor the speed of the fan. 7.1.1 limit and conf iguration registers at power up, all the registers are reset to their de fault values and pwm[1:3] are set to ?fan always on full? mode. before initiating the monitoring cycle for either manual or auto mode, the values in the limit and configuration registers should be set. the limit and configuration registers are: ? registers 54h ? 5bh: tachx minimum ? registers 5fh ? 61h: zone x range/fanx frequency ? registers 5ch ? 5eh: pwmx configuration ? registers 62h ? 63h: pwm x ramp rate control ? registers 64h ? 66h: pwmx minimum duty cycle ? registers 67h ? 69h: zone x low temp limit ? registers 6ah ? 6ch: zone x temp absolute limit ? all fans in auto mode are set to full ? register 81h: tach_pwm association ? registers 90h ? 93h: tachx option registers ? registers 94h ? 96h: pwmx option registers the limit and configuration registers are defined in chapter 8, register set . notes: ? the start bit in register 40h ready/lock/start re gister must be set to ?1? to start temperature monitoring functions. ? setting the pwm configuration register to auto m ode will not take effect until after the start bit is set 7.1.2 device set-up bios will follow the steps listed belo w to configure the f an registers on this device. the registers corresponding to each function are listed. all st eps may not be necessary if default values are acceptable. regardless of all changes made by the bios to the limit and parameter registers during configuration, the emc6d103s will continue to operate based on defaul t values until the start bit, in the ready/lock/start register, is set. once the start bit is set, the emc6d103s will operate according to the values that were set by bios in the limit and parameter registers. 1. set limits and parameters (not necessarily in this order) 2. [5f-61h] set pwm frequencies and auto fan control range. 3. [62-63h] set ramp rate control
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 32 smsc emc6d103s datasheet 4. [5c-5eh] set the fan spin-up delays. 5. [5c-5eh] match each pwm output with a corresponding thermal zone. 6. [67-69h] set the zone temperature low limits. 7. [6a-6ch] set the zone temperature absolute limits. 8. [64-66h] set the pwm minimum duty cycle. 9. [81h] associate a tachometer input to a pwm output register 10. [90-93h] select the tach mode of operation (mode 1 or mode 2) 11. [90-93h] set the number of edges per tach reading 12. [90-93h] set the ignore first 3 edges of tach input bit 13. [90-93h] set the slow bit to 0b if tach r eading should indicated slow fan event as fffeh and 1b if stalled fan event as ffffh. 14. [94-96h] set the tach reading update rate 15. [94-96h] set the tach reading guard time (mode 2 only) 16. [94-96h] set the tach reading logic for opportunistic mode (mode 2 only) 17. [94-96h] set the szen bit, which determines if the pwm output will ramp to off or jump to off. 18. [40h] set bit 0 (start ) to start monitoring. 19. [40h] set bit 1 (lock) to lock the limit and parameter registers (optional) 7.1.3 pwm fan speed control note: the following description applies to pwm1, pwm2, and pwm3. when describing the op eration of the pwms, the terms ?full on? and ?100% duty cycle? means that the pwm output will be high for 255 clocks and low for 1 clock (in vert bit = 0). the exception to this is during fan spin-up when the pwm pin will be fo rced high for the duration of the spin-up time. 7.1.3.1 manual fan control operating mode (test mode) when operating in manual fan control operating mode, software controls the speed of the fans by directly programming the pwm duty cycle. the oper ation of the fans can be monitore d based on reading the temperature and tac hometer reading registers and/or by polling the interrupt status registers. the emc6d103s offers the option of generating an interrupt indicated by the int# signal located on the pwm2 and tach3 pins. to control the pwm outputs in manual mode: ? write ?111? to bits[7:5] zone/mode, located in registers 5ch-5eh: pwmx configuration. ? the speed of the fan is controlled by the duty cyc le set for that pwm output. the duty cycle must be programmed in registers 30h-32h: current pwm duty to monitor the fans: fans equipped with tachometer outputs can be monitored via the tachx input pins. see section 7.1.4, "fan speed monitoring," on page 40 . if an out-of-limit condition occurs, the corresponding status bit will be set in the interrupt status registers. setting this status bit will generate an in terrupt signal on the int# pin (if enabled). software must handle the interrupt condition and modify the operation of the device accordingly. software can evaluate the operation of the fan control devic e through the temperature and fan tachometer reading registers. when in manual mode, the current pwm duty cycle regi sters can be written to adjust the speed of the fans, when the start bit is set. these register s are not writable when the lock bit is set.
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 33 revision 0.2 (06-14-06) datasheet note: the pwmx current duty cycle register is implemented as two separate registers: a read-only and a write-only. when a value is written to this register in manual mode there will be a delay before the programmed value can be read back by software. the hardware updates the read- only pwmx current duty cycl e register on the beginning of a pwm cycle. if ramp rate control is disabled, the delay to read back the programmed value will be from 0 seconds to 1/(pwm frequency) seconds. typically, the delay will be 1/(2*pwm frequency) seconds. 7.1.3.2 auto fan control operating mode the emc6d103s implements automatic fan control. in auto fan mode, this device automatically adjusts the pwm duty cycle of the pwm outp uts, according to th e flow chart on the following page (see figure 7.1 automatic fan control flow diagram on page 34 ). pwm outputs are assigned to a thermal zone bas ed on the pwmx configuration registers (see section 6.10, "thermal zones," on page 30 ). it is possible to have more than one pwm output assigned to a thermal zone. for example, pwm outputs 2 and 3, connected to two chassis fans, may both be controlled by thermal zone 2. at any time, if the temperature of a zone exce eds its absolute limit, all pwm outputs go to 100% duty cycl e to provide maximum cooling to the system (except those fans that are disabled or in manual mode). it is possible to have a single fan controlled by multiple zones, turning on when either zone requires cooling based on its individual settings. a vcc por resets all values to their initial or default states. if the start bit is one, the auto fan control block will evaluate the temperature in the zones configured for each fan in a round robin method. the auto fa n control block completely evaluates the zones for all three fans in a maximum of 0.25sec.
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 34 smsc emc6d103s datasheet figure 7.1 automatic fan control flow diagram *see registers 5c-5eh: pwm configuration on page 62 for details. when in auto fan control operating mode the hardwa re controls the fans directly based on monitoring of temperature and speed. to control the fans: set the minimum temperature that will activate the automatic fan control algorithm. this value is programmed in registers 67h-69h: zone x low temp limit (auto fan mode only). the speed of the fan is controlled by the duty cycle set for that device. the duty cycle for the minimum fan speed must be programmed in registers 64h- 66h: pwmx minimum duty cycle. this value corresponds to the speed of the fan when the temperature reading is equal to the minimum temperature limit setting. as the actual temper ature increases and is above the zone limit temperature and below the absolute temperatur e limit, the pwm will be determined by a linear function based on the auto fan speed range bits in registers 5fh-61h. auto fan mode initiated temp >= abslimit (6a ~6c) override all pwm outputs to 100% duty cycle except if disabled or in manual mode temp >= low limit (67~69) no yes set fan speed based on auto fan range algorithm* no begin fan spin-up yes set fan output to 100% fan spinning up? spin up time elapsed? (5c-5e) yes begin polling cycle end polling cycle no no end fan spin up yes set fan to min pwm (64~ 66) yes no mi n pwm at 0%?
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 35 revision 0.2 (06-14-06) datasheet set the absolute temperature for ea ch zone in registers 6ah-6ch: zone x temp absolute limit (auto fan mode only). if the actual temperature is equal to or exceeds the absolute temperature in one or more of the associated zones, all fans operating in auto mode will be set to full on, regardless of which zone they are operating in (except those that are disabled or configured for manual mode). note: fans can be disabled via the pwmx configur ation registers and the absolute temperature safety feature can be disabled by writing 80h into the zone x temp absolute limit registers. to set the mode to operate in auto mode, set bits[7 :5] zone/mode, located in registers 5ch-5eh: pwm configuration bits[7:5]=?000? for pwm on zone 1; bits[7:5]=?001? for pwm on zone 2; bits[7:5]=?010? for pwm on zone 3. if the ?hottest? option is chosen (101 or 110), then the pwm output is controlled by the zone that results in t he highest pwm duty cycle value. notes: ? software can be alerted of an out-o f-limit condition by the int# pin if a status bit is set and enabled and the interrupt function is enabled on either the pwm2 or tach3 pins ? software can monitor the operation of the fans through the fan tachometer reading registers and by the pwm x current pwm duty registers. it can also monitor current temperature readings through the temperature limit registers if hardware monitoring is enabled. ? fan control in auto mode is implemented without any input from external processor. in auto ?zone? mode, the speed is adjusted automati cally as shown in the following figure. fans are assigned to a zone(s). it is possible to have more than one fan assigned to a thermal zone or to have multiple zones assigned to one fan. figure 7.2 on page 36 shows the control for the auto fan algorithm. the part allows a minimum temperature to be set, below which the fan will run at minimum speed. a temperature range is specified over which the part will automatically adjust the fan speed. if the minimum fan speed is set to 00h, then, when the temperature exceeds the low limi t, the fan will ?spin up? by going on full for a programmable amount of time. following this spin up time, the fan will go to a duty cycle computed by the auto fan algorithm. as the temperature rise s, the duty cycle will increase until the fan is running at full-speed when the temp erature reaches the minimum plus the r ange value. the effect of this is a temperature feedback loop, which will cause the temperature to reach equilibrium between the minimum temperature and the minimum temperature plus the range. provided that the fan has adequate cooling capacity for all environmental a nd power dissipation conditions, this system will maintain the temperature within acceptable limits, while allowing the fan to run slower (and quieter) when less cooling is required.
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 36 smsc emc6d103s datasheet figure 7.2 automatic fan control 7.1.3.3 spin up when a fan is being started from a stationary state (pwm duty cycle =00h), the part will cause the fan to ?spin up? by going to 100% duty cycle for a programmable amount of time to overcome the inertia of the fan (i.e., to get the fan turning). following th is spin up time, the fan will go to the duty cycle computed by the au to fan algorithm. note 7.3 the emc6d103s automatically performs the spin up routine upon power-up. the only conditions that will allow the fan to be in an st ationary state are if the user programs the pwm input to 00h (in manual mode) or the user programs the minimum pwm to 00h and the corresponding temperature channel(s) are below the low temperature limit. during spin-up, the pwm duty cycle is reported as 0%. to limit the spin-up time and thereby reduce fan no ise, the part uses feedba ck from the tachometers to determine when each fan has started spinni ng properly. the following tachometer feedback is included into the auto fan algorithm during spin-up. auto fan operation during spin up: the pwm goes to 100% duty cycle until the tachomet er reading register is below the minimum limit (see figure 7.4 ), or the spin-up time expires, whichever co mes first. this causes spin-up to continue until the tachometer enters the valid count range, unless the spin up time expires. if the spin up expires before the tachometer enters the valid range, an inte rrupt status bit will be set once spin-up expires. note that more than one tachometer may be asso ciated with a pwm, in whic h case all tachometers associated with a pwm must be in the valid range for spin-up to end. pwm min set to 0% t max = t min + t range t min 100% temp duty cycle pwm min set to x% (x is not 0) t max = t min + t range t min 100% temp duty cycle spin-up time min note: when spin-up ends, the pwm is set to the current calculated pwm
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 37 revision 0.2 (06-14-06) datasheet figure 7.4 spin up reduction enabled this feature defaults to enabled; it can be disabled by clearing bit 4 of the configuration register (7fh). if disabled, the all fans go to 100% duty cycle for the durati on of their associated spin up time. note that the tachometer x minimum r egisters must be programmed to a value less than ffffh in order for the spin up reduction to work properly. notes: ? the tachometer reading register always gives the actual reading of the tachometer input. ? no interrupt bits are set during spin-up. 7.1.3.4 hottest option if the ?hottest? option is chosen (101 or 110), t hen the fan is controlled by the limits and parameters associated with the zone that requires the highest pwm duty cycle value, as calculated by the auto fan algorithm. 7.1.3.5 ramp rate control logic the ramp rate control logic, if enabled, limits the amount of change in the pwm duty cycle over a specified period of time. this period of time is programmable in the ramp rate control registers located at offsets 62h and 63h. 7.1.3.5.1 ramp rate cont rol disabled: (default) the auto fan control logic determines the duty cycle for a particular te mperature. if pwm ramp rate control is disabled, the pwm output will be set to this calculated duty cycle. 7.1.3.5.2 ramp rat e control enabled: if pwm ramp rate control is enabled, the pwm duty cycle will ramp up or down to the new duty cycle computed by the auto fan control logic at the programm ed ramp rate. the pwm ramp rate control logic compares th e current duty cycle computed by the au to fan logic with the previous ramp rate duty cycle. if the current duty cycle is gr eater than the previous ra mp rate duty cycle the ramp rate duty cycle is incremented by ?1? at the progra mmed ramp rate until it is greater than or equal to the current calculated duty cycle. if the current duty cycle is less th an the previous ramp rate duty cycle, the ramp rate duty cycle is decremented by ?1? until it is less than or equ al to the current duty cycle. if the current pwm duty cycle is equal to t he calculated duty cycle the pwm output will remain unchanged. note : when spin up reduction is enabled (suren), the spin up time will be less than or equal to the programmed time for spin up. once the tachometer(s) associated with a pwm output are operating within the programmed limits or the spin up time expires, whichever comes first, the pwm output is reduced to the calculated duty cycle. pwm output spin up time tach reading vs. tach limit ffffh tach reading > tach limit tach reading < tach limit duty cycle = 100% duty cycle = 0% programmed spin up time
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 38 smsc emc6d103s datasheet internally, the pwm ramp rate control logic will increment/dec rement the internal pwm duty cycle by ?1? at a rate determined by the ramp rate control register (see register 62h, 63h: pwm ramp rate control on page 66 ). the actual duty cycle output is ch anged once per the period of the pwm output, which is determined by the frequency of the pwm output. (see figure 7.6 illustration of pwm ramp rate control on page 39 .) ? if the period of the pwm output is less than the step size created by the pwm ramp rate, the pwm output will hold the duty cycle constant until the ramp rate logic increm ents/decrements the duty cycle by ?1? again. for example, if the pw m frequency is 87.7hz (1/87.7hz = 11.4msec) and the pwm step time is 206msec, the pwm duty cycle will be held constant for a minimum of 18 periods (206/11.4 = 18.07) until the ramp logic increments/decre ments the actual pwm duty cycle by ?1?. ? if the period of the pwm output is greater than the step size created by the pwm ramp rate, the ramp rate logic will force the pwm output to increment/decre ment the actual duty cycle in increments larger than 1/255. for example, if the pwm frequency is 11hz (1/11hz = 90.9msec) and the pwm step time is 5msec, the pwm duty cycle output will be incremented 18 or 19 out of 255 (i.e., 90 .9/5 = 18.18) until it reac hes the calculated duty cycle. notes: ? the step size may be less if the calculated duty cycle minus the actual duty cycle is less than 18. ? the calculated pwm duty cycle reac ts immediately to a change in the temperature reading value. the temperature reading value may be updated once in 624msec, once in 78msec, once in 223msec (default), or once in 447msec (see table 6.2, ?conversion cycle timing,? on page 22 ). the internal pwm duty cycle generated by the ramp rate control logic gradually ramps up/down to the calculated duty cycle at a rate pre-determined by the value programmed in the pwm ramp rate control bits . the pwm output latches the internal du ty cycle generated by the ramp rate control block every 1/(pwm frequency) seconds to determine the actual duty cycle of the pwm output pin. pwm output transiti on from off to on when the calculated pw m duty cycle generated by t he auto fan control logic transitions from the ?off? state to the ?on? state (i.e., current pwm duty cycle>00h), the internal pwm duty cycle in the ramp rate control logic is initialized to the calculated duty cycle without any ramp time and the pwmx current duty cycle register is set to this value. the pwm output will latch the current duty cycle value in the ramp rate control block to control the pwm output. note 7.5 this event will only occur if the minimum pwm for a particular pwm driver is programmed to be 00h and is either changed (if the pwm driver is configured for manual operating mode) or the temperature rises above the low li mit (if the pwm driver is configured for automatic operating mode). pwm output transition from on to off each pwm output has a control bit to determine if the pwm output will transition immediately to the off state (default) or if it will gradually step down to off at the programmed ramp rate. these control bits (szen) are located in the pwmx options registers at offsets 94h-96h. this transition will only occur in manual mode if the user sets the pwm duty cycle to 0% from a non- zero value. table 7.1 pwm ramp rate rrx-[2:0] pwm ramp time (sec) (time from 33% duty cycle to 100% duty cycle) pwm ramp time (sec) (time from min duty cycle to 100% duty cycle) time per pwm step (pwm step size = 1/255) pwm ramp rate (hz) 000 35 52.53 206 msec 4.85
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 39 revision 0.2 (06-14-06) datasheet figure 7.6 illustration of pwm ramp rate control notes: ? the pwm duty cycle latches the ramping duty cycle on the rising edge of the pwm output. ? the calculated duty cycle, ramping duty cycle, and the pwm output duty cycle are asynchronous to each other, but are all synchronized to the internal 90khz clock source. 001 17.6 26.52 104 msec 9.62 010 11.8 17.595 69 msec 14.49 011 7.0 10.455 41 msec 24.39 100 4.4 6.63 26 msec 38.46 101 3.0 4.59 18 msec 55.56 110 1.6 2.55 10 msec 100 111 0.8 1.275 5 msec 200 table 7.1 pwm ramp rate (continued) rrx-[2:0] pwm ramp time (sec) (time from 33% duty cycle to 100% duty cycle) pwm ramp time (sec) (time from min duty cycle to 100% duty cycle) time per pwm step (pwm step size = 1/255) pwm ramp rate (hz) example 1: pwm period < ramp rate step size pwm frequency = 87.7hz (11.4msec) & pwm ramp rate = 38.46hz (26msec) calculate duty cycle 70h 74h pwm duty cycle 70h 11.4ms 1 1 . 4m s 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 11.4ms 71h 71h 71h 72h 72h 73h 73h 73h 74h 74h 74h example 2: pwm period > ramp rate step size pwm frequency = 11hz (90.9msec) & pwm ramp rate = 38.46hz (26msec) calculate duty cycle 70h 74h ramping duty cycle pwm duty cycle 70h 70h 71h 72h 73h 74h 26ms 26ms 2 6 m s 2 6 m s ramping duty cycle 70h 71h 72h 73h 74h 26ms 26ms 2 6 m s 2 6 m s 90.9msec 71h 74h
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 40 smsc emc6d103s datasheet it should be noted t hat the actual duty cycle on the pin is created by the pwm ramp rate control block and latched on the rising ed ge of the pwm output. therefore, the current pwm duty cycle may lag the pwm calculated duty cycle. 7.1.4 fan speed monitoring the chip monitors the speed of the fans by utilizing fan tachometer input signals from fans equipped with tachometer outputs. the fan tachometer in puts are monitored by using the fan tachometer registers. these signals, as well as the f an tachometer registers, are described below. the tachometers will operate in one of two modes: ? mode 1: standard tachometer reading mode. this mo de is used when the fan is always powered. ? mode 2: enhanced tachometer reading mode. this mode is used when the pwm is pulsing the fan. 7.1.4.1 tach inputs the tachometer inputs are implemented as digital inpu t buffers with logic to filter out small glitches on the tach signal. 7.1.4.2 selecting the mode of operation: the mode is selected through the mode select bits located in the tach option register. this mode select bit is defined as follows: ? 0=mode 1: standard tachometer reading mode ? 1=mode 2 (default): enhanced tachometer reading mode. default mode of operation: ? mode 2 ? slow interrupt disabled (force fffeh) ? tach interrupt enabled via enable bit ? tach limit = ffffh ? look for 5 tach edges ? don?t ignore first 3 edges after guard time ? guard time = 32 clock periods (1 clock period = 1/90khz). ? tach readings updated once a second 7.1.4.3 mode 1 ? always monitoring mode 1 is the simple case. in this mode, the fan is always powered when it is ?on? and the fan tachometer output always has a valid output. this mode is typically used if a linear dc voltage control circuit drives the fan. in this mode, the fan tachometer simply counts the number of 90khz pulses between the programmed number of edges (default = 5 edges). the fan tachometer reading registers are continuously updated. notes: ? some enhanced features added to support mode 2, are available to mode 1 also. they are: programmable number of tach edges and force tach reading register to fffeh to indicate a slow fan. ? five edges or two tach pulses are generated per revolution. the counter is used to determine the period of the fan tachometer input pulse. the counter starts counting on the first edge and continues counting until it detects the last edge or until it reaches ffffh. if the programmed number of edges is detected on or before the counter reaches ffffh, the reading register is updated with that count value. if the counter reaches ffffh and no edges were detected
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 41 revision 0.2 (06-14-06) datasheet a stalled fan event has occurred and the tach reading register will be set to ffffh. if one or more edges are detected, but less than the programmed number of edges, a slow fan event has occurred and the tach reading register will be set to either fffeh or ffffh depending on the state of the slow tach bits located in the tachx options registers at offsets 90h - 93h. software can easily compute the rpm value using the tachometer reading value if it knows the number of edges per revolution. 7.1.4.4 mode 2 ? monitor ta ch input when pwm is ?on? in this mode, the pwm is used to pulse the fan motor of a 3-wire fan. 3-wire fans use the same power supply to drive the fan motor and to drive the tachom eter output logic. when the pwm is ?on? the fan generates valid tach pulses. when the pwm is not driving the fan, the tachometer signal is not generated and the tach signal becomes indeterminate or tristate. therefore, mode 2 only makes tachometer measurements when th e associated pwm is dr iving high during an update cycle. as a result, the fan tachometer measurement is ?synchroni zed? to the pwm output, such that it only looks for tach pulses when the pwm is ?on?. notes: ? high frequency pwm operation is designed for use wi th four wire fans. although some three wire fans are capable of operating with high frequency pwm, the tach output is very difficult to read. external circuitry is required for accurate tach reading of a three wire fan that is driven with high frequency pwm. ? any fan tachometer input may be associated with any pwm output (see linking fan tachometers to pwms on page 46 .) 7.1.4.4.1 assumpti ons (refer to figure 7.7, "pwm and tachometer concept"): the tachometer pulse generates 5 transitions per f an revolution (i.e., two fan tachometer periods per revolution, edges 2 6). one half of a revolution (one tachometer period) is equivalent to three edges (2 4 or 3 5). one quarter of a revolution (one-half tach ometer period) is equivalent to two edges. to obtain the fan speed, count the number of 90khz pulses that occurs between 2 edges i.e., 2 3, between 3 edges i.e., 2 4, or between 5 edges, i.e. 2 6 (the case of 9 edges is not shown). the time from 1-2 occurs through the guard time and is not to be used. for the discussion below, an edge is a high-to-low or low-to-high transition (edge s are numbered ? refer to figure 7.7, "pwm and tachometer concept"). the tachometer circuit begins monitoring the tach when the associated pwm output transitions high and the guard time has expired. each tach circuit will continue monitoring until the programmed number of edges has been detected, whichever comes first. the fan tachometer value may be updated every 300ms, 500ms, or 1000ms.
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 42 smsc emc6d103s datasheet figure 7.7 pwm and tachometer concept 7.1.4.4.2 fan tachomete r options for mode 2 ? 2, 3, 5 or 9 ?edges? to calculate the fan speed ( figure 7.7 ) ? guard time a is programmable (8-63 clocks) to account for delays in the system ( figure 7.7 ) ? the pwm frequencies for modes 1 & 2 are: 11.0 hz , 14.6 hz, 21.9 hz, 29.3 hz, 35.2 hz, 44.0 hz, 58.6 hz, 87.7hz and 25khz ? option to ignore first 3 tachometer edges after guard time ? option to force tach reading register to fffeh to indicate a slow fan. 7.1.4.5 fan tachometer reading registers: the tachometer reading registers are 16 bits, uns igned. when one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a valid reading. the order is lsb first, msb second. the value ffffh indicate s that the fan is not spinning, or the tachometer input is not connected to a valid signal (this could be triggered by a counter overflow). these registers are read only ? a write to these registers has no effect. notes: ? the fan tachometer reading registers always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional. ? ffffh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (this could be triggered by a counter overflow). ? the tachometer registers are read only ? a write to these registers has no effect. ? mode 1 should be enabled and the tachometer limit register should be set to ffffh if a tachometer input is left unconnected. internal pwm signal window for valid tach pulses guard time a tach pulses tach pulses 2 3 4 5 1 6 bd f a ce pwm ?on?
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 43 revision 0.2 (06-14-06) datasheet 7.1.4.6 programming options for each tachometer input the features defined in this section are programmable via the tachx option registers located at offsets 90h-93h and the pwmx option registers located at offsets 94h-96h. 7.1.4.6.1 tach re ading update time in mode 1, the fan tachometer reading regist ers are continuously updated. in mode 2, the fan tachometer registers are updated every 300ms, 500 msec, or 1000msec. this option is programmed via bits[1:0] in the pwmx option register. the pwm associated with a particular tach(s) determines the tach update time. 7.1.4.6.2 pr ogrammed number of tach edges in modes 1 & 2, the number of edges is programmable for 2, 3, 5 or 9 edges (i.e., ? tachometer pulse, 1 tachometer pulse, 2 tachometer pulses, 4 tachomet er pulses). this option is programmed via bits[2:1] in the tachx option register. note: the ?5 edges? case corresponds to two tachometer pulses, or 1 rpm for most fans. using the other edge options will require software to scale the values in the reading register to correspond to the count for 1 rpm. 7.1.4.6.3 guard time (mode 2 only) the guard time is programmable from 8 to 63 clocks (90khz). this option is programmed via bits[4:3] in the tachx option register. 7.1.4.6.4 ignore first 3 ta chometer edges (mode 2 only) option to ignore first 3 tachometer edges after guard time. this option is programmed for each tachometer via bits[2:0] in the tachx option regist er. default is do not ignore first 3 tachometer edges after guard time. 7.1.4.7 summary of operation for modes 1 & 2 the following summarizes the detection cases: ? no edge occurs during the pwm ?on? time: indicate this condition as a stalled fan ? the tachometer reading register contains ffffh. ? one edge (or less than programmed number of edges) occurs during the pwm ?on? time : indicate this condition as a slow fan. ? if the slow bit is set to 0, the tachometer reading register will be set to fffeh to indicate that this is a slow fan instead of a seized fan. note: this operation also pertains to the case where the tachometer counter reaches ffffh before the programmed number of edges occurs. ? if the slow bit is set to one, the tachometer reading register will be set to ffffh. in this case, no distinction is made between a slow or seized fan. note: the slow interrupt feature (slow) is configured in the tachx options registers at offsets 90h to 93h. ? the programmed number of edges occurs: -mode 1: if the programmed number of edges occurs before the counter reaches ffffh latch the tachometer count -mode 2: if the programmed number of edges occurs during the pwm ?on? time: latch the tachometer count. (see note below). notes: ? whenever the programmed number of edges is detected, the edge detection ends and the state machine is reset. the tachometer reading register is updated with the tachometer count value at this time. see note 7.8 below for the one exception to this behavior.
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 44 smsc emc6d103s datasheet note 7.8 this max value will be ffffh if the programmed number of edges is detected when the count reaches ffffh or if no edges are detec ted. if the count reaches ffffh in mode 1 and some edges were detected, but less than the programmed number of edges, the maximum tach count value is determined by the slow interrupt enable bit located in the tachx options registers at offsets 90h to 93h. if slow interrupt detection is set to 0, the count will be forced to fffeh, else the count will be forced to ffffh. 7.1.4.8 examples of mi nimum rpms supported the following tables show minimum rpms that can be supported with the different parameters. the first table uses 3 edges and the second table uses 2 edges. as described in assumptions (refer to figure 7.7, "pwm and tachometer concept"): on page 41 , the tach detection circuitry expects a fan to deliver 5 tach edges per full revolution. when measuring the fan speed using a pwm drive, the slowest fan speed that can be measured is dependent upon how long the pwm drive is high as well as how many edges are being counted to make a valid measurement. the data shown in ta b l e 7 . 2 is taken by measuring 3 tach edges or 1/2 of a single rotation. if the tach signal is seen as a square wave with a fi xed duty cycle and variab le period (where period is inversely proportional to the fan speed), then 3 edges would coincide with a single tach pulse. therefore, in order to accurately measure a tach signal using 3 edges, the pwm must be high for at least as long as the full period of the tach signal. for example, if the pwm frequency is 87.7hz (1st row), then the maximum measurement time available is 11.36msec at 100% duty cycle. this implies, that the ma ximum period that can be measured is also 11.36msec. because period is in versely proportional to fan speed and 1 full period is equivalent to 1/2 a single rotation, this means that the minimum fan speed that can be detected at 100% duty cycle is: the values shown in ta b l e 7 . 2 and table 7.3 include a guard time that occurs immediately after the pwm is set high where the tach pulse is not measured. the effect of this guard time is to reduce the effective ?on? time of the pwm with respect to measuring a tach pulse. table 7.2 minimum rpm detectable using 3 edges pwm frequency pulse width at duty cycle (pwm ?on? time) minimum rpm at duty cycle ( note 7.10 ) (30/t tachpulse ) (hz) 25% (msec) 50% (msec) 100% (msec) ( note 7.9 ) 25% 50% 100% 87.7 2.85 5.7 11.36 10865 5347 2662 58.6 4.27 8.53 17 7175 3554 1774 44 5.68 11.36 22.64 5366 2662 1330 35.2 7.1 14.2 28.3 4279 2126 1063 29.3 8.53 17.06 34 3554 1768 885 21.9 11.42 22.83 45.48 2648 1319 661 14.6 17.12 34.25 68.23 1761 878 440 11 22.73 45.45 90.55 1325 661 332 1 11.36 ms ----------------------- 1 2 -- - rotation 1000 ms s --------------------- - 60 s min --------- - 2641 =
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 45 revision 0.2 (06-14-06) datasheet note 7.9 100% duty cycle is 255/256. note 7.10 rpm=60/t revolution , t tachpulse = t revolution /2. using 3 edges for detection, t tachpulse = (pwm ?on? time ? guard time). minimum rpm values shown use minimum guard time (88.88usec). note 7.11 100% duty cycle is 255/256 note 7.12 rpm=60/t revolution , t tachpulse = t revolution /2. using 2 edges for detection, t tachpulse = 2*(pwm ?on? time-guard time). minimum rpm values shown use minimum guard time (88.88usec). 7.1.4.9 detection of a stalled fan there is a fan failure bit (tachx) in the interrupt status register used to indicate that a slow or stalled fan event has occurred. if the tach reading value exceeds the value programmed in the tach limit register the interrupt status bit is set. see interrupt status register 2 at offset 42h. notes: ? the reading register will be forced to ffffh if a stalled event occurs (i.e., stalled event =no edges detected.) ? the reading register will be forced to either ffffh or fffeh if a slow fan event occurs. (i.e., slow event: 0 < #edges < programmed #edges). if the control bit, slow, located in the tachx options registers at offsets 90h - 93h, is set then fffeh will be forced into the corresponding tach reading register to indicate that the fan is spinning slowly. ? the fan tachometer reading register stays at ffffh in the event of a stalled fan. if the fan begins to spin again, the tachometer logic will reset and latch the next valid reading into the tachometer reading register. 7.1.4.10 fan interrupt status bits the status bits for the fan events are in interrupt status register 2 (42h). these bits are set when the reading register is above the tachometer minimum and the interrupt enable 2 (fan tachs) register bits are configured to enable fan tach events. no interrupt status bits are set for fan events (even if the fan is stalled) if the associated tachometer minimum is set to ffffh (registers 54h-5bh). table 7.3 minimum rpm detectable using 2 edges pwm frequency pulse width at duty cycle (pwm ?on? time) minimum rpm at duty cycle ( note 7.12 ) (30/t tachpulse ) (hz) 25% (msec) 50% (msec) 100% (msec) ( note 7.11 ) 25% 50% 100% 87.7 2.85 5.7 11.36 5433 2673 1331 58.6 4.27 8.53 17 3588 1777 887 44 5.68 11.36 22.64 2683 1331 665 35.2 7.1 14.2 28.3 2139 1063 532 29.3 8.53 17.06 34 1777 884 442 21.9 11.42 22.83 45.48 1324 660 330 14.6 17.12 34.25 68.23 881 439 220 11 22.73 45.45 90.55 663 331 166
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 46 smsc emc6d103s datasheet note: the interrupt enable 2 (fan tachs) register at offset 80h defaults to enabled for the individual tachometer status events bits. the group fan tach int# bit defaults to disabled. this bit needs to be set if fan tach interrupts are to be generated on the external int# pin. see figure 6.3 interrupt control on page 25 . 7.1.5 linking fan ta chometers to pwms the tach/pwm association register at offset 81h is used to associate a tachometer input with a pwm output. this association has three purposes: 1. the auto fan control logic supports a feature called spinup reduction. if spinup reduction is enabled (suren bit), the auto fan control logic will stop driving the pwm output high if the associated tach input is operating within normal parameters. (note: suren bit is located in the configuration register at offset 7fh) 2. to measure the tachometer input in mode 2, the tachometer logic must know when the associated pwm is ?on?. 3. inhibit fan tachometer interrupts when the associated pwm is ?off?. see the description of the pwm_tach register. the default configuration is: pwm1 -> tach1. pwm2 -> tach2. pwm3 -> tach3 & tach4.
smsc emc6d103s 47 revision 0.2 (06-14-06) datasheet chapter 8 register set definition for the lock and start columns: yes = register is made read-only when the related bit is set; no = register is not made read-only when the related bit is set. table 8.1 register summary reg addr read /write reg name bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb default value lock start 20h r +2.5v reading 7 6 5 4 3 2 1 0 n/a no no 21h r vccp reading 7 6 5 4 3 2 1 0 n/a no no 22h r vcc reading 7 6 5 4 3 2 1 0 n/a no no 23h r +5v reading 7 6 5 4 3 2 1 0 n/a no no 24h r +12v reading 7 6 5 4 3 2 1 0 n/a no no 25h r remote diode 1 temp reading 7 6 5 4 3 2 1 0 n/a no no 26h r internal temp reading 7 6 5 4 3 2 1 0 n/a no no 27h r remote diode 2 temp reading 7 6 5 4 3 2 1 0 n/a no no 28h r tach1 lsb 7 6 5 4 3 2 1 0 n/a no no 29h r tach1 msb 15 14 13 12 11 10 9 8 n/a no no 2ah r tach2 lsb 7 6 5 4 3 2 1 0 n/a no no 2bh r tach2 msb 15 14 13 12 11 10 9 8 n/a no no 2ch r tach3 lsb 7 6 5 4 3 2 1 0 n/a no no 2dh r tach3 msb 15 14 13 12 11 10 9 8 n/a no no 2eh r tach4 lsb 7 6 5 4 3 2 1 0 n/a no no 2fh r tach4 msb 15 14 13 12 11 10 9 8 n/a no no 30h r/w note 8.1 pwm1 current duty cycle 7 6 5 4 3 2 1 0 n/a yes note 8.1 no 31h r/w note 8.1 pwm2 current duty cycle 7 6 5 4 3 2 1 0 n/a yes note 8.1 no 32h r/w note 8.1 pwm3 current duty cycle 7 6 5 4 3 2 1 0 n/a yes note 8.1 no 3eh r company id 7 6 5 4 3 2 1 0 5ch no no 3fh r version / stepping ver3 ver2 ver1 ver0 stp3 stp2 stp1 stp0 6ah no no 40h r/w note 8.2 ready/lock/start res res res res ovrid ready lock start 00h yes note 8.2 no
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 48 smsc emc6d103s datasheet 41h r-c note 8.3 interrupt status register 1 int2 d2 amb d1 5v vcc vccp 2.5v 00h no no 42h r-c note 8.3 interrupt status register 2 err2 err1 tach4 tach3 tach2 tach1 res 12v 00h no no 43h r vid0-4 res res res vid4 vid3 vid2 vid1 vid0 n/a no no 44h r/w 2.5v low limit 7 6 5 4 3 2 1 0 00h no no 45h r/w 2.5v high limit 7 6 5 4 3 2 1 0 ffh no no 46h r/w vccp low limit 7 6 5 4 3 2 1 0 00h no no 47h r/w vccp high limit 7 6 5 4 3 2 1 0 ffh no no 48h r/w vcc low limit 7 6 5 4 3 2 1 0 00h no no 49h r/w vcc high limit 7 6 5 4 3 2 1 0 ffh no no 4ah r/w 5v low limit 7 6 5 4 3 2 1 0 00h no no 4bh r/w 5v high limit 7 6 5 4 3 2 1 0 ffh no no 4ch r/w 12v low limit 7 6 5 4 3 2 1 0 00h no no 4dh r/w 12v high limit 7 6 5 4 3 2 1 0 ffh no no 4eh r/w remote diode 1 low temp 7 6 5 4 3 2 1 0 81h no no 4fh r/w remote diode 1 high temp 7 6 5 4 3 2 1 0 7fh no no 50h r/w internal low temp 7 6 5 4 3 2 1 0 81h no no 51h r/w internal high temp 7 6 5 4 3 2 1 0 7fh no no 52h r/w remote diode 2 low temp 7 6 5 4 3 2 1 0 81h no no 53h r/w remote diode 2 high temp 7 6 5 4 3 2 1 0 7fh no no 54h r/w tach1 minimum lsb 7 6 5 4 3 2 1 0 ffh no no 55h r/w tach1 minimum msb 15 14 13 12 11 10 9 8 ffh no no 56h r/w tach2 minimum lsb 7 6 5 4 3 2 1 0 ffh no no 57h r/w tach2 minimum msb 15 14 13 12 11 10 9 8 ffh no no 58h r/w tach3 minimum lsb 7 6 5 4 3 2 1 0 ffh no no 59h r/w tach3 minimum msb 15 14 13 12 11 10 9 8 ffh no no 5ah r/w tach4 minimum lsb 7 6 5 4 3 2 1 0 ffh no no 5bh r/w tach4 minimum msb 15 14 13 12 11 10 9 8 ffh no no 5ch r/w pwm 1 configuration zon2 zon1 zon0 inv res spin2 spin1 spin0 62h yes no 5dh r/w pwm 2 configuration zon2 zon1 zon0 inv res spin2 spin1 spin0 62h yes no 5eh r/w pwm 3 configuration zon2 zon1 zon0 inv res spin2 spin1 spin0 62h yes no 5fh r/w zone 1 range/pwm 1 frequency ran3 ran2 ran1 ran0 frq3 frq2 frq1 frq0 c3h yes no table 8.1 register summary (continued) reg addr read /write reg name bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb default value lock start
smsc emc6d103s 49 revision 0.2 (06-14-06) datasheet 60h r/w zone 2 range/pwm 2 frequency ran3 ran2 ran1 ran0 frq3 frq2 frq1 frq0 c3h yes no 61h r/w zone 3 range/pwm 3 frequency ran3 ran2 ran1 ran0 frq3 frq2 frq1 frq0 c3h yes no 62h r/w pwm1 ramp rate control res res res res rr1e rr1-2 rr1-1 rr1-0 e0h yes no 63h r/w pwm 2, pwm3 ramp rate control rr2e rr2-2 rr2-1 rr2-0 rr3e rr3-2 rr3-1 rr3-0 00h yes no 64h r/w pwm 1 minimum duty cycle 7 6 5 4 3 2 1 0 80h yes no 65h r/w pwm 2 minimum duty cycle 7 6 5 4 3 2 1 0 80h yes no 66h r/w pwm 3 minimum duty cycle 7 6 5 4 3 2 1 0 80h yes no 67h r/w zone 1 low temp limit 7 6 5 4 3 2 1 0 80h yes no 68h r/w zone 2 low temp limit 7 6 5 4 3 2 1 0 80h yes no 69h r/w zone 3 low temp limit 7 6 5 4 3 2 1 0 80h yes no 6ah r/w zone 1 temp absolute limit 7 6 5 4 3 2 1 0 64h yes no 6bh r/w zone 2 temp absolute limit 7 6 5 4 3 2 1 0 64h yes no 6ch r/w zone 3 temp absolute limit 7 6 5 4 3 2 1 0 64h yes no 6fh r/w xor test tree enable res res res res res res res xen 00h yes no 7ch r/w note 8.4 special function register avg2 avg1 avg0 smsc note 8.7 smsc note 8.7 inten mon-md lpmd note 8.5 40h yes note 8.4 no 7dh r reserved res res res res res res res res 00h no no 7eh r/w interrupt enable 1 (voltages) vcc 12v 5v res vccp 25v res volt ech yes no 7fh r/w configuration init smsc note 8.7 smsc note 8.7 suren trdy res p2int t3int 10h yes no 80h r/w interrupt enable 2 (fan tachs) res res res tach4 tach3 tach2 tach1 tach 1eh yes no 81h r/w tach_pwm association t4h t4l t3h t3l t2h t2l t1h t1l a4h yes no 82h r/w interrupt enable 3 (temp) res res res res d2en d1en amb temp 0eh yes no 85h r a/d converter lsbs reg 1 rd2.3 rd2.2 rd2.1 rd2.0 rd1.3 rd1.2 rd1.1 rd1.0 n/a no no 86h r a/d converter lsbs reg 2 v12.3 v12.2 v12.1 v12.0 am.3 am.2 am.1 am.0 n/a no no 87h r a/d converter lsbs reg 3 v50.3 v50.2 v50.1 v50.0 v25.3 v25.2 v25.1 v25.0 n/a no no table 8.1 register summary (continued) reg addr read /write reg name bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb default value lock start
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 50 smsc emc6d103s datasheet note: smsc test registers may be read/write registers. writing these registers can cause unwanted results. note 8.1 the pwmx current duty cycle registers are only writable when the a ssociated fan is in manual mode. in this case, the register i s writable when the start bit is set, but not when the lock bit is set. note 8.2 the lock bit in the ready/lock/start register is locked by the lock bit. the start and ovrid bits are always writable, both whe n the start bit is set and when the lock bit is set. note 8.3 the interrupt status registers are cl eared on a read if no events are active note 8.4 the inten bit in register 7ch is always writable, both when the start bit is set and when the lock bit is set. note 8.5 in shutdown mode (lpmd=1 & start=0) all the h/w monitoring registers/bits are not accessible except for the following: bits[2: 0] in the special function register (sftr) at offset 7ch and bits[7:0] in the configuration register at offset 7fh. note 8.6 these reserved bits are read/write bits. writing these bits to a ?1? has no effect on the hardware. note 8.7 smsc bits may be read/write bits. writing these bits to a value other than the default value may cause unwanted results 88h r a/d converter lsbs reg 4 vcc.3 vcc.2 vcc.1 vcc.0 vcp.3 vcp.2 vcp.1 vcp.0 n/a no no 90h r/w tach1 option res res res 3edg mode edg1 edg0 slow 04h no no 91h r/w tach2 option res res res 3edg mode edg1 edg0 slow 04h no no 92h r/w tach3 option res res res 3edg mode edg1 edg0 slow 04h no no 93h r/w tach4 option res re s res 3edg mode edg1 edg0 slow 04h no no 94h r/w pwm1 option res note 8.6 res note 8.6 opp grd1 grd0 szen updt1 updt0 0ch yes no 95h r/w pwm2 option res note 8.6 res note 8.6 opp grd1 grd0 szen updt1 updt0 0ch yes no 96h r/w pwm3 option res note 8.6 res note 8.6 opp grd1 grd0 szen updt1 updt0 0ch yes no ffh r smsc test register tst7 tst 6 tst 5 tst 4 tst3 tst2 tst1 tst0 n/a no no table 8.1 register summary (continued) reg addr read /write reg name bit 7 msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 lsb default value lock start
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 51 revision 0.2 (06-14-06) datasheet 8.1 undefined registers the registers shown in table 8.1, "register summary" above are the defined registers in the part. any reads to undefined registers always return 00h. writes to undefined registers have no effect and do not return an error. 8.2 defined registers 8.2.1 registers 20-24h: voltage reading the voltage reading registers reflect the current voltage of the emc6d103s voltage monitoring inputs. voltages are presented in the registers at ? full scale for the nominal voltage, meaning that at nominal voltage, each register will read c0h. the voltage reading registers will be updated automatically by the emc6d103s chip with a minimum frequency of 4hz. these registers are read only ? a write to these registers has no effect. 8.2.2 registers 25-27h: temperature reading table 8.2 registers 20-24h: voltage reading register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 20h r +2.5v reading 7 6 5 4 3 2 1 0 n/a 21h r vccp reading 7 6 5 4 3 2 1 0 n/a 22h r vcc reading 7 6 5 4 3 2 1 0 n/a 23h r +5v reading 7 6 5 4 3 2 1 0 n/a 24h r +12v reading 7 6 5 4 3 2 1 0 n/a table 8.3 voltage vs. register reading input nominal voltage register reading at nominal voltage maximum voltage register reading at maximum voltage minimum voltage register reading at minimum voltage +2.5v 2.5v c0h 3.32v ffh 0v 00h vccp 2.25v c0h 3.00v ffh 0v 00h vcc 3.3v c0h 4.38v ffh 0v 00h +5v 5.0v c0h 6.64v ffh 0v 00h +12v 12.0v c0h 16.00v ffh 0v 00h table 8.4 registers 25-27h: temperature reading register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 25h r remote diode 1 temp reading 7 6 5 4 3 2 1 0 n/a 26h r internal temp reading 7 6 5 4 3 2 1 0 n/a 27h r remote diode 2 temp reading 7 6 5 4 3 2 1 0 n/a
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 52 smsc emc6d103s datasheet the temperature reading registers reflect the current temperatures of the internal and remote diodes. remote diode 1 temp reading register reports the temperature measured by the remote1- and remote1+ pins, remote diode 2 temp reading register reports the temperature measured by the remote2- and remote2+ pins, and the internal temp reading register reports the temperature measured by the internal (ambient) temperature s ensor. current temperatures are represented as 8 bit, 2?s complement, signed numbers in celsius, as shown below in ta b l e 8 . 5 . the temperature reading register will return a value of 80h if the remote diode pins are not implemented by the board designer or are not functioning properly (this corresponds to the diode fault interrupt status bits). the temperature reading registers will be updated automatically by the emc6d103s chip with a minimum frequency of 4hz. note: these registers are read only ? a write to these registers has no effect. each of the temperature reading registers are mapped to a zone. each pwm may be programmed to operate in the auto fan control operating mode by associating a pwm with one or more zones. the following is a list of the zone associations. ? zone 1 is controlled by remote diode 1 temp reading ? zone 2 is controlled by internal temp reading (ambient temperature sensor) ? zone 3 is controlled by remote diode 2 temp reading 8.2.3 registers 28-2fh: fan tachometer reading table 8.5 temperature vs. register reading temperature reading (dec) reading (hex) -127 c -127 81h . . . . . . . . . -50 c -50 ceh . . . . . . . . . 0 c 0 00h . . . . . . . . . 50 c 50 32h . . . . . . . . . 127 c 127 7fh (sensor error) 80h table 8.6 registers 28-2fh: fan tachometer reading register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 28h r tach1 lsb 7 6 5 4 3 2 1 0 n/a 29h r tach1 msb 15 14 13 12 11 10 9 8 n/a 2ah r tach2 lsb 7 6 5 4 3 2 1 0 n/a 2bh r tach2 msb 15 14 13 12 11 10 9 8 n/a 2ch r tach3 lsb 7 6 5 4 3 2 1 0 n/a
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 53 revision 0.2 (06-14-06) datasheet the fan tachometer reading registers contain the number of 11.111 s periods (90khz) between full fan revolutions. fans produce two tachometer pulses per full revolution. these registers are updated at least once every second. to convert the value in the tach reading registers to a representative rpm value is a simple mathematical exercise. the 16bit reading is first converted to a decimal number and then multiplied by the clock period (11.11 s). this gives the measured period of two full tach pulses which equals 1 full fan revolution. this number is then inverted and multiplied by 60 to give rotations / minute. for example: if the tach 1 data bytes contain 0c86h (msb followed by lsb). this is equivalent to 3206 clock counts. multiplying this number by 11.111 s (clock period) yields 0.03562s. this number represents the measured time for two full periods of the tach signal. inverting this number and multiplying it by 60 yields a final rpm value of 1684. the larger the returned count, the slower the me asured fan speed. the slowest fan speed that can be stored is approximately 82rpm with an output code of fffdh. this slow speed is not practical to measure in tach monitoring mode 2 (see table 7.2 on page 44 and table 7.3 on page 45 for minimum rpm?s measured using mode 2 and section 7.1.4.4, "mode 2 ? monitor tach input when pwm is ?on?," on page 41 for a description of this monitoring mode). this value is represented for each fan in a 16 bit, unsigned number. the fan tachometer reading registers always return an accurate fan tachometer measurement, even when a fan is disabled or non-functional, including when the start bit=0. when one byte of a 16-bit register is read, the other byte latches the current value until it is read, in order to ensure a valid reading. the order is lsb first, msb second. ffffh indicates that the fan is not spinning, or the tachometer input is not connected to a valid signal (this could be triggered by a counter overflow). fffeh, if the slow bit in the corresponding tachx option register is set (see section 8.2.28, "registers 90h-93h: tachx option registers," on page 75 for details), indicates that fan is spinning, but too slowly to be measured at the current tach settings. these registers are read only ? a write to these registers has no effect. 8.2.4 registers 30-32h: current pwm duty 2dh r tach3 msb 15 14 13 12 11 10 9 8 n/a 2eh r tach4 lsb 7 6 5 4 3 2 1 0 n/a 2fh r tach4 msb 15 14 13 12 11 10 9 8 n/a table 8.7 registers 30-32h: current pwm duty register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 30h r /w (see note 8.8 ) pwm1 current duty cycle 7 6 5 4 3 2 1 0 n/a 31h r /w (see note 8.8 ) pwm2 current duty cycle 7 6 5 4 3 2 1 0 n/a 32h r /w (see note 8.8 ) pwm3 current duty cycle 7 6 5 4 3 2 1 0 n/a table 8.6 registers 28-2fh: fan tachometer reading (continued) register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 54 smsc emc6d103s datasheet note 8.8 these registers are only writable when the associated fan is in manual mode. these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. the current pwm duty registers stor e the duty cycle that the chip is currently driving the pwm signals at. at initial power-on, the duty cycle is 100% and thus , when read, this register will return ffh. after the ready/lock/start register start bit is set, this register and the pwm signals are updated based on the algorithm described in the auto fan control operating mode section and the ramp rate control logic, unless the associated fan is in manual mode ? see below. note: when the device is configured for manual mode, the ramp rate control logic should be disabled. when read, the current pwm duty registers return the current pwm duty cycle for the respective pwm signal. these registers are read only ? a write to these registers has no effect. note: if the current pwm duty cycle registers are writt en while the part is no t in manual mode or when the start bit is zero, the data will be stored in internal registers that will only be active and observable when the start bit is set and the fan is configured for manual mode. while the part is not in manual mode and the start bit is zero, the current pwm duty cycle registers will read back ffh. manual mode (test mode) in manual mode, when the start bit is set to 1 and the lock bit is 0, the current duty cycle registers are writable to control the pwms. note: when the lock bit is set to 1, the current duty cycle registers are read-only. the pwm duty cycle is represented as follows: during spin-up, the pwm duty cycle is reported as 0%. notes: ? the pwmx current duty cycle always reflects the current duty cycle on the associated pwm pin. ? the pwmx current duty cycle register is implem ented as two separate registers: a read-only and a write-only. when a value is written to this register in manual mode there will be a delay before the programmed value can be read back by software . the hardware updates the read-only pwmx current duty cycle register on th e beginning of a pwm cycle. if ramp rate contro l is disabled, the delay to read back the programmed value will be from 0 seconds to 1/(pwm frequency) seconds. typically, the delay will be 1/(2*pwm frequency) seconds. table 8.8 pwm duty vs register reading current duty value (decimal) value (hex) 0% 0 00h ? ? ? 25% 64 40h ? ? ? 50% 128 80h ? ? ? 100% 255 ffh
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 55 revision 0.2 (06-14-06) datasheet 8.2.5 register 3eh: company id the company id register contains the company identification number. this number is a method for uniquely identifying the part manufacturer. this register is read only ? a write to this register has no effect. 8.2.6 register 3fh: version / stepping the four least significant bits of the version / stepping register [3:0] contain the current stepping of the emc6d103s silicon. stepping numbers are to begin from a value of 08h, to indicate that the register set is enhanced from previous hardware monitoring standards. the four most significant bits [7:4] reflect the version number, which will be fixed at 0110b. for the a0 stepping of this device, the register will read 01101000b. for the a1 stepping, this register will read 01101001b and so on. the register is used by application software to identify which device has been implemented in the given system. based on this information, software can de termine which registers to read from and write to. further, application software may use the current stepping to implement work-arounds for bugs found in a specific silicon stepping. this register is read only ? a write to this register has no effect. 8.2.7 register 40h: read y/lock/start monitoring setting the lock bit makes the lock bit read only. table 8.9 register 3eh: company id register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 3eh r company id 7 6 5 4 3 2 1 0 5ch table 8.10 register 3fh: version / stepping register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 3fh r version / stepping ver3 ver 2 ver 1 ver 0 stp 3 stp 2 stp 1 stp0 6ah table 8.11 register 40h: ready/lock/start monitoring register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 40h r/w ready/lock/start res res res res ovrid ready lock start 00h
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 56 smsc emc6d103s datasheet note: there is a start-up time of up to 82ms for monitoring after the start bit is set to ?1?, during which time the reading registers are not valid. the following summarizes the operation of the part based on the start bit: 1. if start bit = '0' then: a. fans are set to full on. b. no voltage, temperature, or fan tach monitoring is performed. the values in the reading registers will be n/a (not applicable), which means these values will not be considered valid readings until the start bit = '1'. the exception to this is the ta chometer reading registers, which always give the actual reading on the tach pins. c. no status bits are set. 2. if start bit = '1' d. all fan control and monitoring will be based on the current values in the registers. there is no need to preserve the default values after software has programmed these registers because no monitoring or auto fan control will be done when start bit = '0'. e. status bits may be set. f. setting the start bit to 1 does not prevent the limit and parameter registers from being written. note: once programmed, the register values will be saved when start bit is reset to ?0?. table 8.12 ready/lock/start monitoring bit name r/w default description 0 start r/w 0 when software writes a 1 to this bit, the emc6d103s enables monitoring and pwm output control functions based on the limit and parameter registers. before this bit is set, the part does not update register values. whenever this bit is set to 0, the monitoring and pwm output control functions are based on the default limits and parameters, regardless of the current values in the limit and parameter registers. the emc6d103s preserves the values currently stored in the limit and parameter registers when this bit is set or cleared. this bit is not affected by setting the lock bit. note: when this bit is 0, all fans are on full 100% duty cycle, i.e., pwm pins are high for 255 clocks, low for 1 clock. when this bit is 0, the part is not monitoring. 1 lock r/w 0 setting this bit to 1 lo cks specified limit and para meter registers. once this bit is set, limit and parameter registers become read only and will remain locked until the device is powe red off. this register bit becomes read only once it is set. 2 ready r 0 the emc6d103s sets this bit automatically after the part is fully powered up, has completed the power-up-reset process, and after all a/d converters are functioning (all bias conditions for the a/ds have stabilized and the a/ds are in operational mode). (always reads back ?1?.) 3 ovrid r/w 0 if this bit is set to 1, all pwm outputs go to 100% duty cycle regardless of whether or not the lock bit is set. 4-7 reserved r 0 reserved.
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 57 revision 0.2 (06-14-06) datasheet 8.2.8 register 41h: interr upt status register 1 note 8.9 this register is cleared on a read if no events are active. note: the individual enable bits for d2, amb, and d1 are located in the interrupt enable 3 (temp) register at offset 82h. the individual enable bits for5v, 2.5v, vcc, and vccp, are located in the interrupt enable 1 register at offset 7eh. the interrupt status register 1 bits are automatically set by the device, if enabled, whenever the 2.5v, vccp, 3.3v, or 5v input voltages violate the limits set in the limit and parameter registers or when the measured temperature violates the limits set in the limit and parameter registers for any of the three thermal inputs. this register holds a bit set until the event is read by software or until the individual enable bit is cleared (see note below). the contents of this regi ster are cleared (set to 0) automatically by the emc6d103s after it is read by software, if the voltage or temperature no longer violates the limits set in the limit and parameter registers. once set, the interrupt status register 1 bits remain set until a read event occurs or until the individual enable bits is cleared, even if the voltage or temperature no longer violate the limits set in the limit and parameter registers. note that clearing the group temp, fan, or volt enable bits or the global inten enable bit has no effect on the status bits. see registers 44-4dh: voltage limit registers on page 60 and on page 60 . this register contains a bit that indicates that a bit is set in the other interrupt status register. if bit 7 is set, then a status bit is set in the interrupt status register 2. therefore, s/w can poll this register, and only if bit 7 is set does the other register need to be read. this bit is cleared (set to 0) automatically by the device if there are no bits set in interrupt status registers 2. this register is read only ? a write to this register has no effect. note: clearing the individual enable bits: 1. an interrupt status bit will never change from a 0 to a 1 when the corresponding individual interrupt enable bit is cleared (set to 0), regardless of whether the limits are violated during a measurement. 2. if the individual enable bit is cleared while the associated status bit is 1, the status bit will be cleared when the associated reading register is updated. the reading registers only get updated when the start bit is set to ?1?. if the enable bit is cleared when the start bit is 0, the associated interrupt status bit will not be cleared until the start bit is set to 1 and the associated reading register is updated. table 8.13 register 41h: interrupt status register 1 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 41h r-c (see note 8.9 ) interrupt status 1 int2 d2 amb d1 5v vcc vccp 2.5v 00h
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 58 smsc emc6d103s datasheet 8.2.9 register 42h: interrupt status register 2 note 8.10 this register is cleared on a read if no events are active. this register is read only ? a write to this register has no effect. the interrupt status register 2 bits are automatical ly set by the device whenever a remote temperature sensor error occurs, a tach reading value is above the minimum value set in the tachometer minimum registers, or whenever the 12v input voltage violates the limits set in the limit and parameter registers. the interrupt status register 2 register holds a set bit until the event is read by software or until the individual interrupt enable bit is cleared (see note below). the contents of this register are clear ed (set to 0) automatically by the emc6d103s after it is read by software, if the voltage no longer violate the limits set in the limit and parameter registers, if the temperature sensor error no loner exists, or if the tach reading register is no longer above the minimum. once set, the interrupt status register 2 bits remain set until a read event occurs or until the individual interrupt enable bit is cleared, even if the voltage, tach, or diode event no longer exists. table 8.14 interrupt status register 1 bit name r/w default description 0 2.5v_error r 0 the emc6d103s automatically sets this bit to 1 when the 2.5v input voltage is less than or equal to the limit set in the 2.5v low limit register or greater than the limit set in the 2.5v high limit register. 1 vccp_error r 0 the emc6d103s automatically sets this bit to 1 when the vccp input voltage is less than or equal to the limit set in the vccp low limit register or greater than the limit set in the vccp high limit register. 2 vcc_error r 0 the emc6d103s automatically sets this bit to 1 when the vcc input voltage is less than or equal to the limit set in the vcc low limit register or greater than the limit set in the vcc high limit register. 3 5v_error r 0 the emc6d103s automatically sets this bit to 1 when the 5v input voltage is less than or equal to the limit set in the 5v low limit register or greater than the limit set in the 5v high limit register. 4 remote diode 1 limit error r 0 the emc6d103s automatically sets this bit to 1 when the temperature input measured by the remote1- and remote1+ is less than or equal to the limit set in the remote diode 1 low temp register or greater than the limit set in remote diode 1 high temp register. 5 internal sensor limit error r 0 the emc6d103s automatically sets this bit to 1 when the temperature input measured by the internal temper ature sensor is less than or equal to the limit set in the internal low temp register or greater than the limit set in the internal high temp register. 6 remote diode 2 limit error r 0 the emc6d103s automatically sets this bit to 1 when the temperature input measured by the remote2- and remote2+ is less than or equal to the limit set in the remote diode 2 low temp register or greater than the limit set in the remote diode 1 high temp register. 7 int2 event active r 0 the device automatically sets this bit to 1 when a status bit is set in the interrupt status register 2. table 8.15 register 42h: interrupt status register 2 register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 42h r-c (see note 8.10 ) interrupt status register 2 err2 err1 tach4 tach3 tach2 tach1 res 12v 00h
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 59 revision 0.2 (06-14-06) datasheet the remote diode fault bits do not clear on a read while the fault condition exists. if the start bit is set when a fault condition occurs, 80h will be loaded into the associated temperature reading register, which will cause the associated diode limit error bit to be set (remote diode 1 limit error or remote diode 2 limit error) in addition to the diode fault bit. disabling the enable bit for the diode will clear both the fault bit and the error bit for that diode (see note below). this register is read only ? a write to this register has no effect. note: clearing the individual enable bits. 1. an interrupt status bit will never change from a 0 to a 1 when the corresponding individual interrupt enable bit is cleared (set to 0), regardless of whether the limits are violated during a measurement. 2. if the individual enable bit is cleared while the associated status bit is 1, the status bit will be cleared when the associated reading register is updated. the reading registers only get updated when the start bit is set to ?1?. if the enable bit is cleared when the start bit is 0, the associated interrupt status bit will not be cleared until the start bit is set to 1 and the associated reading register is updated. 8.2.10 register 43h: vid the vid register contains the values of emc6d103s vid0-vid4 input pins. this register indicates the status of the vid lines that interconnect the processor to the voltage regulator module (vrm). table 8.16 interrupt status register 2 bit name r/w def ault description 0 +12v_error r 0 the emc6d103s automatically sets this bit to 1 when the 12v input voltage is less than or equal to the limit set in the 12v low limit register or greater than the limit set in the 12v high limit register. 1 reserved r 0 reserved 2 tach1 slow/stalled r 0 the emc6d103s automatically sets this bit to 1 when the tach1 input reading is above the value set in the tach1 minimum msb and lsb registers. 3 tach2 slow/stalled r 0 the emc6d103s automatically sets this bit to 1 when the tach2 input reading is above the value set in the tach2 minimum msb and lsb registers. 4 tach3 slow/stalled r 0 the emc6d103s automatically sets this bit to 1 when the tach3 input reading is above the value set in the tach3 minimum msb and lsb registers. 5 tach4 slow/stalled r 0 the emc6d103s automatically sets this bit to 1 when the tach4 input reading is above the value set in the tach4 minimum msb and lsb registers. 6 remote diode 1 fault r 0 the emc6d103s automatically sets this bit to 1 when there is either a short or open circuit fault on the remote1+ or remote1- thermal diode input pins as defined in the section diode fault on page 25 . note: if the start bit is set and a fault condition exists, the remote diode 1 reading register will be forced to 80h. 7 remote diode 2 fault r 0 the emc6d103s automatically sets this bit to 1 when there is either a short or open circuit fault on the remote2+ or remote2- thermal diode input pins as defined in the section diode fault on page 25 . note: if the start bit is set and a fault condition exists, the remote diode 2 reading register will be forced to 80h. table 8.17 register 43h: vid register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 43h r vid0-4 res res res vid4 vid3 vid2 vid1 vid0 n/a
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 60 smsc emc6d103s datasheet software uses the information in this register to determine the voltage that the processor is designed to operate at. with this information, software can then dynamically determine the correct values to place in the vccp low limit and vccp high limit registers. this register is read only ? a write to this register has no effect. 8.2.11 registers 44-4dh: voltage limit registers setting the lock bit has no effect on these registers. if a voltage input either exceeds the value set in the voltage high limit register or falls below or equals the value set in the voltage low limit register, the corresponding bit will be set automatically by the emc6d103s in the interrupt status registers (41-42h). voltages are presented in the registers at ? full scale for the nominal voltage, meaning that at nominal voltage, each input will be c0h, as shown in table 8.19 . 8.2.12 registers 4e-53h: te mperature limit registers table 8.18 registers 44-4dh: voltage limit registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 44h r/w 2.5v low limit 7 6 5 4 3 2 1 0 00h 45h r/w 2.5v high limit 7 6 5 4 3 2 1 0 ffh 46h r/w vccp low limit 7 6 5 4 3 2 1 0 00h 47h r/w vccp high limit 7 6 5 4 3 2 1 0 ffh 48h r/w vcc low limit 7 6 5 4 3 2 1 0 00h 49h r/w vcc high limit 7 6 5 4 3 2 1 0 ffh 4ah r/w 5v low limit 7 6 5 4 3 2 1 0 00h 4bh r/w 5v high limit 7 6 5 4 3 2 1 0 ffh 4ch r/w 12v low limit 7 6 5 4 3 2 1 0 00h 4dh r/w 12v high limit 7 6 5 4 3 2 1 0 ffh table 8.19 voltage limits vs. register setting input nominal voltage register setting at nominal voltage maximum voltage register setting at maximum voltage minimum voltage register setting at minimum voltage 2.5v 2.5v c0h 3.32v ffh 0v 00h vccp 2.25v c0h 3.00v ffh 0v 00h vcc 3.3v c0h 4.38v ffh 0v 00h 5v 5.0v c0h 6.64v ffh 0v 00h 12v 12.0v c0h 16.00v ffh 0v 00h table 8.20 registers 4e-53h: temperature limit registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 4eh r/w remote diode 1 low temp 7 6 5 4 3 2 1 0 81h 4fh r/w remote diode 1 high temp 7 6 5 4 3 2 1 0 7fh 50h r/w internal low temp 7 6 5 4 3 2 1 0 81h
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 61 revision 0.2 (06-14-06) datasheet setting the lock bit has no effect on these registers. if an external temperature input or the internal temp erature sensor either exceeds the value set in the high limit register or is less than or equal to the value set in the low limit register, the corresponding bit will be set automatically by the emc6d103s in the interrupt status register 1 (41h). for example, if the temperature reading from the remote1- and remote1+ inputs exceeds the remote diode 1 high temp register limit setting, bit[4] d1 of the interrupt status register 1 will be set. the temperature limits in these registers are represented as 8 bit, 2?s complement, signed numbers in celsius, as shown below in table 8.21 . 8.2.13 registers 54-5bh: fan tachometer low limit 51h r/w internal high temp 7 6 5 4 3 2 1 0 7fh 52h r/w remote diode 2 low temp 7 6 5 4 3 2 1 0 81h 53h r/w remote diode 2 high temp 7 6 5 4 3 2 1 0 7fh table 8.21 temperature limits vs. register settings temperature limit (dec) limit (hex) -127 c -127 81h . . . . . . . . . -50 c-50 ceh . . . . . . . . . 0 c0 00h . . . . . . . . . 50 c50 32h . . . . . . . . . 127 c 127 7fh table 8.22 registers 54-5bh: fan tachometer low limit register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 54h r/w tach1 minimum lsb 7 6 5 4 3 2 1 0 ffh 55h r/w tach1 minimum msb 15 14 13 12 11 10 9 8 ffh 56h r/w tach2 minimum lsb 7 6 5 4 3 2 1 0 ffh 57h r/w tach2 minimum msb 15 14 13 12 11 10 9 8 ffh 58h r/w tach3 minimum lsb 7 6 5 4 3 2 1 0 ffh 59h r/w tach3 minimum msb 15 14 13 12 11 10 9 8 ffh 5ah r/w tach4 minimum lsb 7 6 5 4 3 2 1 0 ffh 5bh r/w tach4 minimum msb 15 14 13 12 11 10 9 8 ffh table 8.20 registers 4e-53h: temperature limit registers (continued)
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 62 smsc emc6d103s datasheet setting the lock bit has no effect on these registers. the fan tachometer low limit registers indicate the tachometer reading that, if exceeded, the corresponding bit will be set in the interrupt status register 2 register. this register represents a number of clock counts between the programmed num ber of tach edges and therefore as the number increases, the effective rpm that it represents will decrease. the limit represents a fixed fan speed (though the tach measurement options may lim it fan speeds that can be measured). see section 8.2.3 for a description of the tach data formatting. in auto fan control mode, the fan can run at high speeds (100% duty cycle), so care should be taken in software to ensure that the limit is low enough not to cause sporadic alerts. note that an interrupt status event will be generated when the tachometer reading is greater than the minimum tachometer limit. the fan tachometer will not cause a bit to be set in the interrupt status register if the current value in the associated current pwm duty registers is 00h or if the pwm is disabled via the pwm configuration register. interrupts will never be generated for a fan if its tachometer minimum is set to ffffh. 8.2.14 registers 5c-5eh: pwm configuration these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. bits [7:5] zone/mode bits [7:5] of the pwm configuration registers associate each pwm with a temperature sensor. ? when in auto fan mode, the pwm will be assi gned to a zone, and it s pwm duty cycle will be adjusted according to the temperature of that zone. if ?hottest? option is selected (101 or 110), the pwm will be controlled by the hottest of zones 2 and 3, or of zones 1, 2, and 3. if one of these options is selected, the pwm is controlled by the limits and parameters for the zone that requires the highest pwm duty cycle, as co mputed by the auto fan algorithm. ? when in manual control mode, the pwmx current duty cycle registers (30h-32h) become read/write. it is then possible to control the pwm outputs with software by writing to these registers. see pwmx current duty cycle registers description. ? when the fan is disabled (100) the corresponding pwm output is driven low (or high, if inverted). ? when the fan is full on (011) the corresponding pwm output is driven high (or low, if inverted). notes: ? zone 1 is controlled by remote diode 1 temp reading register ? zone 2 is controlled by internal temp reading register ? zone 3 is controlled by remote diode 2 temp reading register table 8.23 registers 5c-5eh: pwm configuration register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 5ch r/w pwm 1 configuration zon2 zon1 zon0 inv res spin2 spin1 spin0 62h 5dh r/w pwm 2 configuration zon2 zon1 zon0 inv res spin2 spin1 spin0 62h 5eh r/w pwm 3 configuration zon2 zon1 zon0 inv res spin2 spin1 spin0 62h
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 63 revision 0.2 (06-14-06) datasheet bit [4] pwm invert bit [4] inverts the pwm output. if set to 1, 100% duty cycle will yi eld an output that is low for 255 clocks and high for 1 clock. if set to 0, 100% duty cycle will yield an output that is high for 255 clocks and low for 1 clock. bit [3] reserved bits [2:0] spin up bits [2:0] specify the ?spin up? time for the fan. when a fan is being started from a stationary state, the pwm output is held at 100% duty cycle for th e time specified in table 8.25, "fan spin-up register" before scaling to a lower speed. note: during spin-up, the pwm pin is forced high for the duration of the spin-up time (i.e., 100% duty cycle = 256/256). note: to reduce the spin-up time, this device has implemented a feature referred to as spin up reduction. spin up reduction uses feedback from the tachometers to determine when each fan has started spinning properly. spin up for a pwm will end when the tachometer reading register is below the minimum limit, or the spin-up time expires, whichever comes first. all tachs associated with a pwm must be below min. for spin-up to end prematurely. this feature can be disabled by clearing bit 4 (suren) of the configuration register (7fh). if disabled, the all fans go on full for the duration of their associated spin up time. note that the tachx minimum registers must be programmed to a value less than ffffh in order for the spin-up reduction to work properly. table 8.24 fan zone setting zon[7:5] pwm configuration 000 fan on zone 1 auto 001 fan on zone 2 auto 010 fan on zone 3 auto 011 fan always on full 100 fan disabled 101 fan controlled by hottest of zones 2,3 110 fan controlled by hottest of zones 1,2,3 111 fan manually controlled table 8.25 fan spin-up register spin[2:0] spin up time 000 0 sec 001 100ms 010 250ms (default) 011 400ms 100 700ms 101 1000ms 110 2000ms 111 4000ms
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 64 smsc emc6d103s datasheet 8.2.15 registers 5f-61h: zone temperature range, pwm frequency these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. in auto fan mode, when the temperature for a zone is above the low temperature limit (registers 67-69h) and below the absolute temperature limit (registers 6a-6ch) the speed of a fan assigned to that zone is determined as follows by the auto fan control logic. when the temperature reaches the temperature value programmed in the zone x low temp limit register, the pwm output assigned to that zone is at pwmx minimum duty cycle. between zone x low temp limit and (zone x low temp limit + zone x range), the pwm duty cycle increases linearly according to the temperature as shown in the figure below. figure 8.11 fan activity above low temp limit example for pwm1 assigned to zone 1: ? zone 1 low temp limit (register 67h) is set to 50 c (32h). ? zone 1 range (register 5fh) is set to 8 c (7h) ? pwm1 minimum duty cycle (register 64h) is set to 50% (80h) in this case, the pwm1 duty cycle will be 50% at 50 c . since ( zone 1 low temp limit ) + ( zone 1 range ) = 50 c + 8 c = 58 c , the fan controlled by pwm1 will run at 100% duty cycle when the temper ature of the zone 1 sensor is at 58 c. since the midpoint of the fan control range is 54 c, and the median duty cycle is 75% (halfway between the pwm minimum and 100%), pwm1 duty cycle would be 75% at 54 c. above ( zone 1 low temp limit ) + ( zone 1 range ), the duty cycle must be 100%. table 8.26 registers 5f-61h: zone temperature range, pwm frequency register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 5fh r/w zone 1 range / fan 1 frequency ran3 ran2 ran1 ran0 frq3 frq2 frq1 frq0 c3h 60h r/w zone 2 range / fan 2 frequency ran3 ran2 ran1 ran0 frq3 frq2 frq1 frq0 c3h 61h r/w zone 3 range / fan 3 frequency ran3 ran2 ran1 ran0 frq3 frq2 frq1 frq0 c3h temperature below fan temp limit: fan at fan pwm minimum temperature low limit: output at min fan low limit+ range: output at 100% duty pwm duty is linear this range
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 65 revision 0.2 (06-14-06) datasheet the pwm frequency bits [3:0] determine the pwm frequency for the fan. pwm frequency selection (default =0011=29.3hz) range selection (default =1100=32 c) note: the range numbers will be used to calculate the slope of the pwm ramp up. for the fractional entries, the pwm will go on full when the temp reaches the next integer value e.g., for 3.33, pwm will be full on at (min. temp + 4). table 8.27 register setting vs. pwm frequency freq[3:0] pwm frequency 0000 11.0 hz 0001 14.6 hz 0010 21.9 hz 0011 29.3 hz (default) 0100 35.2 hz 0101 44.0 hz 0110 58.6 hz 0111 87.7 hz 1000 - 1001 n/a 1010 ~25 khz 1011 - 1111 n/a table 8.28 register setting vs. temperature range ran[3:0] range ( c) 0000 2 0001 2.5 0010 3.33 0011 4 0100 5 0101 6.67 0110 8 0111 10 1000 13.33 1001 16 1010 20 1011 26.67 1100 32 1101 40 1110 53.33 1111 80
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 66 smsc emc6d103s datasheet 8.2.16 register 62h, 63h: pwm ramp rate control these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. the duty cycle will be set to the minimum fan duty cycle when the measured temperature falls below the temperature limit register setting for the corresponding pwm. description of ramp rate control bits: if the remote1 or remote2 pins are connected to a processor or chipset, instantaneous temperature spikes may be sampled by the part. the auto fan control logic calculates the pwm duty cycle for all temperature readings. if ramp rate control is disabled, the pwm output will jump or oscillate between different pwm duty cycles causing the fan to suddenly change speeds, which creates unwanted fan noise. if enabled, the pwm ramp rate control logic will prevent the pwm output from jumping, instead the pwm will ramp up/down toward s the new duty cycle at a pre-determined ramp rate. ramp rate control the ramp rate control logic limits the amount of change to the pwm duty cycle over a period of time. this period of time is programmable via the ramp rate control bits. for a detailed description of the ramp rate control bits see ta b l e 8 . 3 0 . for a description of the ramp rate control logic see ramp rate control logic on page 37 . note: ? rr1e, rr2e, and rr3e enable pwm ramp rate control for pwm 1, 2, and 3 respectively. ? rr1-2, rr1-1, and rr1-0 contro l ramp rate time for pwm 1 ? rr2-2, rr2-1, and rr2-0 contro l ramp rate time for pwm 2 ? rr3-2, rr3-1, and rr3-0 contro l ramp rate time for pwm 3 table 8.29 register 62h, 63h: min/off, pwm ramp rate control register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 62h r/w pwm 1 ramp rate control res res res res rr1e rr1-2 rr1-1 rr1-0 e0h 63h r/w pwm 2, pwm 3 ramp rate control rr2e rr2-2 rr2-1 rr2-0 rr3e rr3-2 rr3-1 rr3-0 00h table 8.30 pwm ramp rate control rrx-[2:0] pwm ramp time (sec) (time from 33% duty cycle to 100% duty cycle) pwm ramp time (sec) (time from 0% duty cycle to 100% duty cycle) time per pwm step (pwm step size = 1/255) pwm ramp rate (hz) 000 35 52.53 206 msec 4.85 001 17.6 26.52 104 msec 9.62 010 11.8 17.595 69 msec 14.49 011 7.0 10.455 41 msec 24.39 100 4.4 6.63 26 msec 38.46 101 3.0 4.59 18 msec 55.56
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 67 revision 0.2 (06-14-06) datasheet 8.2.17 registers 64-66h: minimum pwm duty cycle these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. these registers specify the mi nimum duty cycle that the pw m will output when the measured temperature reaches the temper ature limit register setting in auto fan control mode. 8.2.18 registers 67-69h: zone low temperature limit 110 1.6 2.55 10 msec 100 111 0.8 1.275 5 msec 200 table 8.31 registers 64-66h: minimum pwm duty cycle register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 64h r/w pwm1 minimum duty cycle 7 6 5 4 3 2 1 0 80h 65h r/w pwm2 minimum duty cycle 7 6 5 4 3 2 1 0 80h 66h r/w pwm3 minimum duty cycle 7 6 5 4 3 2 1 0 80h table 8.32 pwm duty vs. register setting minimum pwm duty value (decimal) value (hex) 0% 0 00h . . . . . . . . . 25% 64 40h . . . . . . . . . 50% 128 80h . . . . . . . . . 100% 255 ffh table 8.33 registers 67-69h: zone low temperature limit register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value table 8.30 pwm ramp ra te control (continued) rrx-[2:0] pwm ramp time (sec) (time from 33% duty cycle to 100% duty cycle) pwm ramp time (sec) (time from 0% duty cycle to 100% duty cycle) time per pwm step (pwm step size = 1/255) pwm ramp rate (hz)
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 68 smsc emc6d103s datasheet these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. these are the temperature limits for the individual zones. when the current temperature equals this limit, the fan will be turned on if the minimum pwm is set to 00h. when the temperature exceeds this limit, the fan speed will be increased according to the auto fan algorithm based on the setting in the zone x range / pwmx frequency register. default = -127 c=80h application note: all three zone low temperature limit registers must be programmed to a valid value (other than 80h) to allow the autofan control to operate. 8.2.19 registers 6a-6ch: absolute temperature limit these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. in auto fan mode, if any zone associated with a pwm output exceeds the temperature set in the absolute limit register, all pwm outputs will increase their duty cycle to 100% except those that are 67h r/w zone 1 low temp limit 7 6 5 4 3 2 1 0 80h 68h r/w zone 2 low temp limit 7 6 5 4 3 2 1 0 80h 69h r/w zone 3 low temp limit 7 6 5 4 3 2 1 0 80h table 8.34 temperature limit vs. register setting limit limit (dec) limit (hex) -127 c -127 81h . . . . . . . . . -50 c-50 ceh . . . . . . . . . 0 c0 00h . . . . . . . . . 50 c50 32h . . . . . . . . . 127 c 127 7fh table 8.35 registers 6a-6ch: absolute temperature limit register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 6ah r/w zone 1 temp absolute limit 7 6 5 4 3 2 1 0 64h 6bh r/w zone 2 temp absolute limit 7 6 5 4 3 2 1 0 64h 6ch r/w zone 3 temp absolute limit 7 6 5 4 3 2 1 0 64h table 8.33 registers 67-69h: zone low temperature limit
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 69 revision 0.2 (06-14-06) datasheet disabled via the pwm configuration registers. this is a safety feature that attempts to cool the system if there is a potentially catastrophic thermal event. if an absolute limit register set to 80h (-128 c), the safety feature is disabled for the associated zone. that is, if 80h is written into the zone x temp absolute limit register, then regardless of the reading register for the zone, the fans will not turn on-full based on the absolute temp condition. default =100 c=64h. when any fan is in auto fan mode, then if the temperature in any zone exceeds absolute limit, all fans go to full, including any in manual mode, except those that are disabled. therefore, even if a zone is not associated with a fan, if that zone exceeds abs olute, then all fans go to full. in this case, the absolute limit can be chosen to be 7fh for those zones that are not associated with a fan, so that the fans won't turn on unless the temperature hits 127 degrees. 8.2.20 register 6f: xor test register this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. the part incorporates an xor tree test mode. when the test mode is enabled by setting the ?xen? bit high via smbus, the part enters xor test mode. the following signals are included in the xor test tree: ? tach1, tach2, tach3, tach4 ? pwm2, pwm3 since the test mode is xor tree, the order of the signals in the tree is not important. sda and scl are not included in the test tree. table 8.36 absolute limit vs. register setting absolute limit abs limit (dec) abs limit (hex) -127 c -127 81h . . . . . . . . . -50 c-50 ceh . . . . . . . . . 0 c0 00h . . . . . . . . . 50 c50 32h . . . . . . . . . 127 c 127 7fh table 8.37 register 6f: xor test register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 6fh r/w xor test register res res res res res res res xen 00h
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 70 smsc emc6d103s datasheet 8.2.21 register 7ch: sp ecial function register this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. this register contains the following bits: . table 8.38 register 7ch: special function register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 7ch r/w special function avg2 avg1 avg0 smsc smsc inten monmd lpmd 40h table 8.39 special function register bit name r/w default description 0 lpmd r/w 0 low power mode select. ? ?0? = sleep mode ? ?1? = low power mode 1 monmd r/w 0 monitoring mode select. ? ?0? = continuous mode ? ?1? = cycle mode 2 inten r/w 0 global interrupt enable. when set enables the int# pin output function. 3 smsc r/w 0 smsc - writing this bit may have undesired affects. 4 smsc r/w 0 smsc - writing this bit may have undesired affects. 5 avg0 r/w 0 the avg[2:0] bits determine the amount of averaging for each of the six measurements that are performed by the hardware monitor before the reading registers are updated ( table 8.40, "avg[2:0] bit decoder" ). the avg[2:0] bits are priority encoded where the most significant bit has highest priority. for example, when the avg2 bit is asserted, 32 averages will be performed for each measurement before the reading registers are updated regardless of the state of the avg[1:0] bits. note: the default for the avg[2:0] bits is ?010?b 6 avg1 r/w 1 7 avg2 r/w 0 table 8.40 avg[2:0] bit decoder sftr[7:5] averages per reading avg2 avg1 avg0 rem diode 1 rem diode 2 internal diode all voltage readings (+2.5v, +5v, +12v, vccp, and vcc) 0 0 0 128 128 8 8 001 16 16 1 1 01x 16 16 16 16 1xx 32 32 32 32
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 71 revision 0.2 (06-14-06) datasheet 8.2.22 register 7eh: inte rrupt enable 1 register this register becomes read only when the lock bit is set. any further attempts to write to this register shall have no effect. this register is used to enable individual voltage error events to set the corresponding status bits in the interrupt status registers. this register also contains the group voltage enable bit (bit[0] volt), which is used to enable voltage events to force the interrupt pin (int#) low if interrupts are enabled (see bit[2] inten of the special function register at offset 7ch). see figure 6.3 interrupt control on page 25 . this register contains the following bits: 8.2.23 register 7fh: configuration register these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. table 8.41 register 7eh: interrupt enable 1 register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 7eh r/w interrupt enable 1 (voltages) vcc 12v 5v res vccp 25v res volt ech table 8.42 interrupt enable 1 register bits bit name r/w default description 0 volt r/w 0 group int# voltage enable - when set, enables out-of-limit voltages to drive the int# pin low (provided that the inten bit in the special function register is also set). 1 reserved r/w 0 reserved 2 25v r/w 1 when set, enables 2.5v channel to update status registers and generate interrupts 3 vccp r/w 1 when set enables vccp channel to update status registers and generate interrupts 4 reserved r/w 0 reserved 5 5v r/w 1 when set, enables 5v channel to update status registers and generate interrupts 6 12v r/w 1 when set, enables 12v channel to update status registers and generate interrupts 7 vcc r/w 1 when set, enables vcc channel to update status registers and generate interrupts. table 8.43 register 7fh: configuration register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 7fh r/w configuration init smsc smsc suren trdy res p2int t3int 10h
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 72 smsc emc6d103s datasheet this register contains the following bits: 8.2.24 register 80h: inte rrupt enable 2 register these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. this register is used to enable individual fan tach error events to set the corresponding status bits in the interrupt status registers. this register also contains the group fan tach enable bit (bit[0] tach), which is used to enable fan tach events to force the interrupt pin (int#) low if interrupts are enabled (see bit[2] inten of the special function register at offset 7ch). see figure 6.3 interrupt control on page 25 . this register contains the following bits: table 8.44 configuration register bits bit name r/w default description 0 t3int r/w 0 determines functionality of the tach3/int# pin. ? ?0? - tach3 input ? ?1?- int# output 1 p2int r/w 0 determines the functionality of the pwm2/int# pin. ? ?0? - pwm2 output. ? ?1? - int# output. 2 reserved r/w 0 reserved 3 trdy r 0 temperature reading ready - indicates that the temperature reading registers hold valid values. 4 suren r/w 1 spin-up reduction enable - when set, this bit enables the reduction of the spin-up time based on feedback from all fan tachometers associated with each pwm. 5 smsc r/w 0 smsc - writing to this bit to a value different from the default value may cause unwanted results. 6 smsc r/w 0 smsc - writing this bit to a value different than the default value may cause unwanted results. 7 init r/w 0 setting the init bit to ?1? performs a soft reset. this bit is self-clearing. soft reset sets all the registers e xcept the reading registers to their default values. table 8.45 register 80h: interrupt enable 2 register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 80h r/w interrupt enable 2 (fan tachs) res res res tach4 tach3 tach2 tach1 tach 1eh
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 73 revision 0.2 (06-14-06) datasheet 8.2.25 register 81h: tach _pwm association register these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. this register is used to associate a pwm with a tachometer input. this association is used by the fan logic to determine when to prevent a bit from being set in the interrupt status registers. the fan tachometer will not cause a bit to be set in the interrupt status register: g. if the current value in current pwm duty registers is 00h or h. if the fan is disabled via the fan configuration register. note: a bit will never be set in the interrupt status for a fan if its tachometer minimum is set to ffffh. see bit definition below. table 8.46 interrupt enable 2 register bits bit name r/w default description 0 tach r 0 group tach int# enable- when set enables out-of-limit tach measurements assert the int# pin. 1 tach1 r 1 when set, enables the tach1 tachometer to update status registers and generate interrupts. 2 tach2 r 1 when set, enables the tach2 tachometer to update status registers and generate interrupts. 3 tach3 r 1 when set, enables the tach3 tachometer to update status registers and generate interrupts. 4 tach4 r 1 when set, enables the tach4 tachometer to update status registers and generate interrupts. 5 res r/w 0 reserved 6 res r/w 0 reserved 7 res r/w 0 reserved table 8.47 register 81h: tach_pwm association register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 81h r/w tach_pwm association t4h t4l t3h t3l t2h t2l t1h t1l a4h table 8.48 tach_pwm association register bits bit name r/w default description 0 t1l r/w 0 determine which pwm outputs are associated with the tach1 input. see table 8.49 1 t1h r/w 0 2 t2l r/w 1 determine which pwm outputs are associated with the tach2 input. see table 8.49 3 t2h r/w 0 4 t3l r/w 0 determine which pwm outputs are associated with the tach3 input. see table 8.49 5 t3h r/w 1 6 t4l r/w 0 determine which pwm outputs are associated with the tach4 input. see table 8.49 7 t4h r/w 1
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 74 smsc emc6d103s datasheet notes: ? any pwm that has no tach inputs associated with it must be configured to operate in mode 1. ? all tach inputs must be associated with a pwm output. if the tach is not being driven by the associated pwm output it should be configured to operate in mode 1 and the associated tach interrupt must be disabled. 8.2.26 register 82h: inte rrupt enable 3 register these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. this register is used to enable individual thermal error events to set the corresponding status bits in the interrupt status registers. this register also contains the group thermal enable bit (bit[0] temp), which is used to enable thermal events to force the interrupt pin (int#) low if interrupts are enabled (see bit[2] inten of the special function register at offset 7ch). see figure 6.3 interrupt control on page 25 . this register contains the following bits: : table 8.49 pwm assignment bit combinations bits[1:0], bits[3:2], bits[5:4], bits[7:6] pwm associated with tachx 00 pwm1 01 pwm2 10 pwm3 11 reserved table 8.50 register 82h: interrupt enable 3 register register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 82h r/w interrupt enable 3 (temp) res res res res d2en d1en amb temp 0eh table 8.51 interrupt enable 3 register bits bit name r/w default description 0 temp r/w 0 group temperature enable bit - when set, allows temperature channels to assert the int# pin. 1 amb r/w 1 when set, enables the ambient temperature monitor to update the status registers and generate interrupts. 2 d1en r/w 1 when set, enables the remote diode 1 temperature monitor to update the status registers and generate interrupts. 3 d2en r/w 1 when set, enables the remote diode 2 temperature monitor to update the status registers and generate interrupts. 4 res r/w 0 reserved 5 res r/w 0 reserved 6 res r/w 0 reserved 7 res r/w 0 reserved
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 75 revision 0.2 (06-14-06) datasheet 8.2.27 registers 85h-88h: a/ d converter lsbs registers there is a 10-bit analog to digital converter (a dc) located in the hardware monitoring block that converts the measured voltages into 10-bit reading values. depending on the averaging scheme enabled, the hardware monitor may take multiple readings and average them to create the values stored in the reading registers (i.e., 16x averaging, 32x averaging, etc.) the 8 msb?s of the reading values are placed in the reading registers. when the upper 8-bits located in the reading registers are read the 4 lsb?s are latched into their respective bits in the a/d converter lsbs register. this give 12-bits of resolution with a minimum value of 1/16 th per unit measured. (i.e., temperature range: -127.9375 oc < temp < 127.9375 oc and voltage range: 0 < voltage < 256.9375) . see the dc characteristics for the accuracy of the reading values. the eight most significant bits of the 12-bit averaged readings are stored in reading registers and compared with limit registers. the interrupt stat us register bits are asserted if the corresponding measured value(s) on the inputs violate their programmed limits. 8.2.28 registers 90h-93h: tachx option registers these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. table 8.52 registers 85h-88h: a/d converter lsbs registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 85h r a/d converter lsbs reg 1 rd2.3 rd2.2 rd2.1 rd2.0 rd1.3 rd1.2 rd1.1 rd1.0 n/a 86h r a/d converter lsbs reg 2 v12.3 v12.2 v12.1 v12.0 am.3 am.2 am.1 am.0 n/a 87h r a/d converter lsbs reg 3 v50.3 v50.2 v50.1 v50.0 v25.3 v25.2 v25.1 v25.0 n/a 88h r a/d converter lsbs reg 4 vcc.3 vcc.2 vcc.1 vcc.0 vcp.3 vcp.2 vcp.1 vcp.0 n/a register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 90h r/w tach1 option reserved 3edg mode edg1 edg0 slow 04h 91h r/w tach2 option reserved 3edg mode edg1 edg0 slow 04h 92h r/w tach3 option reserved 3edg mode edg1 edg0 slow 04h 93h r/w tach4 option reserved 3edg mode edg1 edg0 slow 04h
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 76 smsc emc6d103s datasheet 8.2.29 registers 94h-96h: pwmx option registers these registers become read only when the lock bit is set. any further attempts to write to these registers shall have no effect. table 8.53 tach option register bits bit name r/w default description 0 slow r/w 0 ? ?0? - force tach reading register to fffeh if number of tach edges detected is greater than 0 but less than the programmed number of edges ? ?1? - force tach reading register to ffffh if number of tach edges detected is greater than 0 but less than the programmed number of edges 1 edg0 r/w 0 determines the number of edges necessary for a valid tach reading. ? 00 = 2 edges ? 01 = 3 edges ? 10 = 5 edges ? 11 = 9 edges 2 edg1 r/w 1 3 mode r/w 0 determines tach reading mode ? ?0? mode 1 - standard operating mode ? ?1? mode 2 - only check measure tach while pwm output is high. 4 3edg r/w 0 this bit is used when the tach mode is configured for mode 2 only. ? ?0? - don?t ignore 1st 3 tach edges after pwm transitions from low to high ? ?1? - ignore first 3 edges after guard time note: this bit has been added to support a small sampling of fans that emit irregular tach pulses when the pwm transitions ?on?. typically, the guard time is sufficient for most fans. 5 res r/w 0 reserved 6 res r/w 0 reserved 7 res r/w 0 reserved table 8.54 registers 94h-96h: pwmx option registers register address read/ write register name bit 7 (msb) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (lsb) default value 94h r/w pwm1 option res res opp grd1 grd0 szen updt1 updt0 0ch 95h r/w pwm2 option res res opp grd1 grd0 szen updt1 updt0 0ch 96h r/w pwm3 option res res opp grd1 grd0 szen updt1 updt0 0ch
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 77 revision 0.2 (06-14-06) datasheet table 8.55 pwm option register bits bit name r/w default description 0 updt0 r/w 0 determines the update rate of tachometer circuits associated with this pwm driver. ? 00 - once a second ? 01 - twice a second ? 1x - every 300msec. 1 updt1 r/w 0 2 szen r/w 1 snap to zero - determines if the pwm output ramps down to 00hor if is immediately set to 00h when the input is set to 00h. ? ?0? - step down the pwm output to off at the programmed ramp rate. ? ?1? - transition pwm output to off immediately when the duty cycle is set to 00h. 3 grd0 r/w 1 sets the guard time that the tachomet er associated with this pwm driver will wait after a transition from low to high before it begins measuring. ? 00 = 63 clocks (90khz clock ~ 700us) ? 01 = 32 clocks (90khz clock ~356us) ? 10 = 16 clocks (90khz clock ~178us) ? 11 = 8 clocks (90khz clock ~89us) 4 grd1 r/w 0 5 opp r/w 0 opportunistic mode enable - when set, enables opportunistic mode. the tachometer reading is updated any time a valid tachometer reading can be made. if a valid readi ng is detected prior to the update cycl e, then the update counter is reset. 6 res r/w 0 reserved 7 res r/w 0 reserved table 8.56 pwm/tach test register bits bit name r/w default description 0 glitch r/w 1 is used to select the glitch suppression logic on the tachometer inputs ? ?0? tach inputs are synchronized to 90khz oscillator. ? ?1? tach inputs are deglitched and synchronized to 90khz oscillator 1 psync1 r/w 0 determine how each pwm outputs exit spinup. ? ?0? - exit spinup asynchronously to the pwm duty cycle. the first pwm period when spinup is terminate may be a partial period. ? ?1? - exit spinup at the beginnin g of the next pwm duty cycle period. this option gets rid of the initial partial period created by exiting spinup, but it extends the spinup time beyond the programmed limit. 2 psync2 r/w 0 3 psync3 r/w 0 4 rovr r/w 1 determines the rollover value for mode 1 (all tachs) ?0? 0080h - useful for simulation ?1? ffffh 5 pwm1_256/ 64 r/w 1 scale the pwm duty cycle for the corresponding channel. when enabled, will shift the pwm duty cycle down by 2 creating a duty cycle with a resolution of 1/256. this allows the device to support higher pwm frequencies ? ?0?= 64 count pwm duty cycl e - resolution is 1/64 ? ?1? = 256 count pwm duty cycle 6 pwm2_256/ 64 r/w 1 7 pwm3_256/ 64 r/w 1
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 78 smsc emc6d103s datasheet chapter 9 timing diagrams 9.1 pwm outputs the following section shows the timing for the pwm[1:3] outputs. figure 9.1 pwmx output timing note 9.2 this value is programmable by the pwm frequency bits located in the frfx registers. note 9.3 the pwm high time is based on a percentage of the total pwm period (min=0/256*t pwm , max =255/256*t pwm ). during spin-up the pwm high time can reach a 100% or full on. (t pwm = t1). table 9.1 timing for pwm[1:3] outputs name description min typ max units t1 pwm period ( note 9.2 ) 0.04 90.9 msec t2 pwm high time ( note 9.3 ) 0 99.6 % t1 t2 fanx
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 79 revision 0.2 (06-14-06) datasheet 9.2 smbus interface figure 9.4 smbus timing note 9.5 the smbus timing (e.g., max clock frequency of 400khz) specified exceeds that specified in the system management bus specification, rev 1.1. this corresponds to the maximum clock frequency for fast mode devices on the i 2 c bus. see ?the i 2 c bus specification,? version 2.0, dec. 1998. note 9.6 at 400khz, spikes of a maximum pulse width of 50ns must be suppressed by the input filter. note 9.7 if using 100 khz clock frequency, the next data bit output to the sda line will be 1250 ns (1000 ns (t r max) + 250 ns (t su : dat min) @ 100 khz) before the sclk line is released. table 9.2 smbus timing symbol parameter limits units comments min max fsmb smb operating frequency 10 400 khz note 9.5 tsp spike suppression 50 ns note 9.6 tbuf bus free time between stop and start condition 1.3 s thd:sta hold time after (repeated) start condition. after this period, the first clock is generated. 0.6 s tsu:sta repeated start condition setup time 0.6 s tsu:sto stop condition setup time 0.6 s thd:dat data hold time 0.3 0.9 s tsu:dat data setup time 100 ns note 9.7 tlow clock low period 1.3 s thigh clock high period 0.6 s tf clock/data fall time 20+0.1c b 300 ns tr clock/data rise time 20+0.1c b 300 ns c b capacitive load for each bus line 400 pf p t buf t r t hd;sta p s s t hd;sta t low t hd;dat t high t f t su;dat t su;sta t su;sto sclk sda
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 80 smsc emc6d103s datasheet chapter 10 mechanical specifications figure 10.1 24-pin ssop package outline, 0.150? wide body, 0.025? pitch notes: 1. controlling unit: inch. 2. tolerance on the true position of the leads is 0.0035 inches maximum. 3. package body dimensions d and e1 do not include the mold protrusion. maximum mold protrusion is 0.006 inches for ends, and 0.010 inches for sides. 4. dimension for foot length l measured at the gauge plane 0.010 inches above the seating plane. 5. details of pin 1 identifier are optional but must be located within the zone indicated. table 10.1 24-pin ssop package parameters min nominal max remarks a 0.053 ~ 0.069 overall package height a1 0.004 ~ 0.010 standoff a2 ~ ~ 0.061 body thickness d 0.337 ~ 0.344 x body size e 0.228 ~ 0.244 y span e1 0.150 ~ 0.157 y body size h 0.007 ~ 0.010 lead frame thickness l 0.016 0.025 0.050 lead foot length e 0.025 basic lead pitch 0 o ~8 o lead foot angle w 0.008 0.010 0.012 lead width ccc ~ ~ 0.004 coplanarity
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 81 revision 0.2 (06-14-06) datasheet appendix a adc voltage conversion table a.1 analog-to-digital voltage conversions for hardware monitoring block input voltage a/d output 12 v in 5 v in v cc 2.5 v in v ccpin decimal binary <0.062 <0.026 <0.0172 <0.013 <0.012 0 0000 0000 0.062?0.125 0.026?0.052 0.017?0.034 0.013?0.026 0.012?0.023 1 0000 0001 0.125?0.188 0.052?0.078 0.034?0.052 0.026?0.039 0.023?0.035 2 0000 0010 0.188?0.250 0.078?0.104 0.052?0.069 0.039?0.052 0.035?0.047 3 0000 0011 0.250?0.313 0.104?0.130 0.069?0.086 0.052?0.065 0.047?0.058 4 0000 0100 0.313?0.375 0.130?0.156 0.086?0.103 0.065?0.078 0.058?0.070 5 0000 0101 0.375?0.438 0.156?0.182 0.103?0.120 0.078?0.091 0.070?0.082 6 0000 0110 0.438?0.500 0.182?0.208 0.120?0.138 0.091?0.104 0.082?0.093 7 0000 0111 0.500?0.563 0.208?0.234 0.138?0.155 0.104?0.117 0.093?0.105 8 0000 1000 ??????? 4.000?4.063 1.666?1.692 1.100?1.117 0.833?0.846 0.749?0.761 64 (1/4 scale) 0100 0000 ??????? 8.000?8.063 3.330?3.560 2.200?2.217 1.667?1.680 1.499?1.511 128 (1/2 scale) 1000 0000 ??????? 12.000?12.063 5.000?5.026 3.300?3.317 2.500?2.513 2.249?2.261 192 (3/4 scale) 1100 0000 ??????? 15.312?15.375 6.380?6.406 4.210?4.230 3.190?3.203 2.869?2.881 245 1111 0101 15.375?15.437 6.406?6.432 4.230?4.245 3.203?3.216 2.881?2.893 246 1111 0110 15.437?15.500 6.432?6.458 4.245?4.263 3.216?3.229 2.893?2.905 247 1111 0111 15.500?15.563 6.458?6.484 4.263?4.280 3.229?3.242 2.905?2.916 248 1111 1000 15.625?15.625 6.484?6.510 4.280?4.300 3.242?3.255 2.916?2.928 249 1111 1001 15.625?15.688 6.510?6.536 4.300?4.314 3.255?3.268 2.928?2.940 250 1111 1010 15.688?15.750 6.536?6.562 4.314?4.330 3.268?3.281 2.940?2.951 251 1111 1011 15.750?15.812 6.562?6.588 4.331?4.348 3.281?3.294 2.951?2.964 252 1111 1100 15.812?15.875 6.588?6.615 4.348?4.366 3.294?3.307 2.964?2.975 253 1111 1101 15.875?15.938 6.615?6.640 4.366?4.383 3.307?3.320 2.975?2.987 254 1111 1110 >15.938 >6.640 >4.383 >3.320 >2.988 255 1111 1111
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 82 smsc emc6d103s datasheet appendix b example fan circuits the following figures show examples of circuitry on the board for the pwm outputs, tachometer inputs, and remote diodes. figure b.1, "fan drive circuitry (apply to pwm driving two fans)" shows how the part can be used to control four fans by connecting two fans to one pwm output. note: these examples represent the minimum requi red components. some designs may require additional components. figure b.1 fan drive circuitry (apply to pwm driving two fans) mmbt390 4 mmbt222 2 mmbt222 2 2.2k 1k 3.3v 3.3v fan 1 fan 2 m m 12 v pwmx
fan control device with high frequency pwm support and hardware monitoring features datasheet smsc emc6d103s 83 revision 0.2 (06-14-06) datasheet figure b.2 fan drive circuitry (a pply to pwm driving one fan) figure b.3 fan tachometer circuitry (apply to each fan) mmbt2222 470 3.3v fan m 12v pwmx note : for fans controlled directly by a pwm, it is suggested to implement the optional diode (d1) to protect the tachometer input from large voltage spikes generated by the fan. 10k 3.3v tach output from fan tach input d1 in4148
fan control device with high frequency pwm support and hardware monitoring features datasheet revision 0.2 (06-14-06) 84 smsc emc6d103s datasheet figure b.4 remote diode (apply to remote2 lines) notes: 1. 2.2nf cap is optional and should be placed close to the emc6d103s if used. 2. the voltage at pwm3 must be at least 2.0v to avoid triggering address enable. 3. the remote diode + and remote diode - tracks should be kept cl ose together, in parallel with grounded guard tracks on each side. using wide trac ks will help to minimize inductance and reduce noise pickup. a 10 mil track minimum width and spacing is recommended. see figure b.5, "suggested minimum track width and spacing". . figure b.5 suggested minimum track width and spacing remote diode + remote diode - 2.2nf external temperature sensing diode (mmbt3904) gnd gnd d+ d- 10 mil. 10 mil. 10 mil. 10 mil. 10 mil. 10 mil. 10 mil.

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